2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012) 2012
DOI: 10.1109/icecs.2012.6463693
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Design comparison of low-power rectifiers dedicated to RF energy harvesting

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Cited by 29 publications
(20 citation statements)
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“…The voltage generated across C p during the charging phase at the second stage can be obtained by substituting (14) in (13). It will result as,…”
Section: Proposed Cascading Schemementioning
confidence: 99%
See 2 more Smart Citations
“…The voltage generated across C p during the charging phase at the second stage can be obtained by substituting (14) in (13). It will result as,…”
Section: Proposed Cascading Schemementioning
confidence: 99%
“…Hence, referring to (13), (17) and using the principle of recursion analysis, the voltage, which will appear across C s1 at the start of the charging phase of Nth stage will be given by,…”
Section: Proposed Cascading Schemementioning
confidence: 99%
See 1 more Smart Citation
“…Moreover the design utilized the native CMOS device which is available in TSMC 0.18 um CMOS process and two bulk connections; bulk connected to source and bulk connected to drain. The source voltage for a 900 MHz frequency is set to 390 mV [10]. The design procedure is shown in Fig.…”
Section: Design Of Ac-dc Converter Using Multi-stage Half-wave Rectifiermentioning
confidence: 99%
“…Many researches focus on modifying present rectifier and voltage multiplier topologies to achieve higher gain, sensitivity, efficiency [52,[55][56][57]61]. For instance, the voltage multiplier achieved maximum 11% PCE at −24 dBm (4 µW) in [62] and 41% PCE at −20.6 dBm (8.7 µW) input power in [57]. While the majority of publications utilized 0.18 µm CMOS technology in their work, [52] applied commercial 40 nm CMOS process to build a low-voltage operation voltage multiplier that reached 44% PCE at 390 mV input.…”
Section: Pros and Cons Of Schottky Diode And Cmos Technologymentioning
confidence: 99%