The voltage multiplier (VM) circuit is a cascade arrangement designed from a series of rectifiers to obtain high DC output voltage. In this classical approach, the DC voltage which is getting generated in the present stage contributes to the next stage. This phenomenon is recurring at every stage resulting into higher DC output voltage than previous. The proposed signaling scheme enables the use of the rectified DC voltage/stage in a classical way along with the involvement of instantaneous input RF voltage. As a result, higher output DC voltage and improved power conversion efficiency (PCE) will be achieved as compared to a conventional VM circuit signaling scheme. The conventional VM circuit used in this work was designed by stacked series arrangement of three standard differential drive rectifiers. Similarly, the proposed VM circuit was formed by implementing proposed signaling scheme into the conventional VM circuit. These architectures were implemented in a standard 0.18 lm CMOS technology The measurements were done by using input RF signal frequency of 433 MHz for resistive load values of 30, 100 KX, and 1 MX respectively. The measured results show that the proposed VM scheme has 22-32 % better power conversion efficiency than the conventional VM scheme.