Design consideration of a static memory cell

Anami, Keiko; Yoshimoto, Masahiko; Shinohara, Hirofumi; Hirata, Yoshinori; Nakano, T.

doi:10.1109/jssc.1983.1051965

Cited by 38 publications

(8 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The stability analysis of an SRAM cell has been a topic of great interest for more than a couple of decades, due to its importance in obtaining high yields for microprocessor and SoC designs. A rich and well developed theory exists for static stability analysis of an SRAM cell [65,66,46]. In [66], the authors proved the formal equivalence of four different criterion for worst-case static noise margin.…”

Section: Iv-b Related Previous Workmentioning

confidence: 99%

Analysis and Design of Resilient VLSI Circuits

Garg¹

2010

View full text Add to dashboard Cite

The reliable operation of Integrated Circuits (ICs) has become increasingly difficult to achieve in the deep sub-micron (DSM) era. With continuously decreasing device feature sizes, combined with lower supply voltages and higher operating frequencies, the noise immunity of VLSI circuits is decreasing alarmingly. Thus, VLSI circuits are becoming more vulnerable to noise effects such as crosstalk, power supply variations and radiationinduced soft errors. Among these noise sources, soft errors (or error caused by radiation particle strikes) have become an increasingly troublesome issue for memory arrays as well as combinational logic circuits. Also, in the DSM era, process variations are increasing at an alarming rate, making it more difficult to design reliable VLSI circuits. Hence, it is important to efficiently design robust VLSI circuits that are resilient to radiation particle strikes and process variations. The work presented in this dissertation presents several analysis and design techniques with the goal of realizing VLSI circuits which are tolerant to radiation particle strikes and process variations.This dissertation consists of two parts. The first part proposes four analysis and two design approaches to address radiation particle strikes. The analysis techniques for the radiation particle strikes include: an approach to analytically determine the pulse width and the pulse shape of a radiation induced voltage glitch in combinational circuits, a technique to model the dynamic stability of SRAMs, and a 3D device-level analysis of the radiation tolerance of voltage scaled circuits. Experimental results demonstrate that the

show abstract

Section: Iv-b Related Previous Workmentioning

confidence: 99%

Analysis and Design of Resilient VLSI Circuits

Garg¹

2010

View full text Add to dashboard Cite

show abstract

“…There are strict constraints on the size of transistors to receive a suitable beta ratio in a conventional 6T SRAM cell [6]. It becomes harder to ensure a favorable SNM in a read operation when the supply voltage is lowering.…”

Section: T Sram Cellmentioning

confidence: 99%

“…It's necessary to constraint the size of transistors in order to maintain the data stability and functionality of a conventional 6T SRAM cell. Dynamic power is a good way to meet the demand of cell stability and low energy consumption [6]. A new eight-transistor SRAM cell using unilateral reading mechanism and combining dynamic power method is proposed in this paper.…”

Section: Introductionmentioning

confidence: 99%

Novel asymmetric 8T SRAM cell with dynamic power

Hang

Zhang

2012

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology

View full text Add to dashboard Cite

Data stability, power consumption and delay are important issues with the scaling of CMOS technology. An asymmetric eight-transistor SRAM cell with improved static-noise margin (SNM) is proposed. In this new 8T SRAM cell, unilateral reading mechanism and dynamic power scheme are combined. Results are validated by HSPICE simulation using 45nm PTM model. The simulated results of the SNM, the power consumption, the propagation delay and the power delay product (PDP) are compared between the dynamic power 6T SRAM cell and the proposed 8T SRAM cell.

show abstract

“…Figure 12 also illustrates the simulated effects of photo misalignment and process bias on the tolerance level of removable charge. For a set level of removed charge, a higher cell ratio is required to maintain cell stability when pulldown transistors M3 and M4 (see , [2], and [3] were measured at VWL =2.OV, 2.5V, and 3.OV respectively. …”

Section: The Effects Of Cell Ratio On Required Data Storage Voltage Lmentioning

confidence: 99%

<title>Implications of scaling on static RAM bit cell stability and reliability</title>

et al. 1993

View full text Add to dashboard Cite

In order to lower manufacturing costs and increase performance, static random access memory (SRAM) bit cells are scaled progressively toward submicron geometries. The reliability of an SRAM is highly dependent on the bit cell stability. Smaller memory cells with less capacitance and restoring current make the array more susceptible to failures from defectivity, alpha hits. and other instabilities and leakage mechanisms. Improving long term reliability while migrating to higher density devices makes the task of building in and improving reliability increasingly difficult. Reliability requirements for high density SRAMs are very demanding with failure rates of less than 100 failures per billion device hours (100 FITs) being a common criteria. Design techniques for increasing bit cell stability and manufacturability must be implemented in order to build in this level of reliability. Several types of analyses are performed to benchmark the performance of the SRAM device. Examples of these analysis techniques which are presented here include DC parametric measurements of test structures, functional bit mapping of the circuit used to characterize the entire distribution of bits, electrical microprobing of weak and/or failing bits, and system and accelerated soft error rate measurements. These tests allow process and design improvements to be evaluated prior to implementation on the final product. These results are used to provide comprehensive bit cell characterization which can then be compared to device models and adjusted accordingly to provide optimized cell stability versus cell size for a particular technology. The result is designed in reliability which can be accomplished during the early stages of product development.

show abstract

Design consideration of a static memory cell

Cited by 38 publications

References 4 publications

Analysis and Design of Resilient VLSI Circuits

Analysis and Design of Resilient VLSI Circuits

Novel asymmetric 8T SRAM cell with dynamic power

<title>Implications of scaling on static RAM bit cell stability and reliability</title>

Contact Info

Product

Resources

About