Design considerations for low gain amplifier in the MDAC of digitally calibrated pipelined ADCs

Adel, Hussein; Louërat, Marie-Minerve; Sabut, Marc

doi:10.1109/vlsi-soc.2013.6673239

Cited by 2 publications

(2 citation statements)

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“….T he gain error mismatch between the channels is minimized in [7] by using a LMS adaptive algorithm. Once the gains are matched, the error corresponding to the 4th segment of the stage residue in channel will be input-independent and (10) becomes: (11) For deterministic multistage calibration, the errors of the first stage will affect the error detection process of the subsequent calibrated stages, and thus analysis and modified procedures are needed to perform accurate multistage calibration. Considering the calibration of the second pipelined stage in the ADC, and due to the difference in the output residues of the 1st split stages, inputs to both 2nd split stages are not the same as shown in Fig.…”

Section: Multistage Split Adc Calibration:operation and Analysismentioning

confidence: 99%

“…These variations can be tracked and compensated for in the background by the proposed calibration scheme with its very fast calibration cycle. In addition of the rapid calibration tracking, and to ensure minimum linearity degradation due to gain variation, the amplifier gain is made 44 dB to preserve the ADC SNDR above 68 dB with gain variation, as discussed in [11].…”

Section: Table I Calibration Time Comparison With Prior Artmentioning

confidence: 99%

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Split ADC Based Fully Deterministic Multistage Calibration for High Speed Pipeline ADCs

Adel

Sabut

Louërat

2015

IEEE Trans. Circuits Syst. I

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A fully deterministic digital background calibration for pipeline ADCs is presented. The proposed approach is based on split ADC concept to give the shortest background calibration time with high accuracy. A slope mismatch averaging technique is employed in a multistage calibration scheme to deterministically detect the circuit errors without any iterative operations or feedback loops, which render it fast and accurate. Analysis and behavioral simulations for the developed multistage calibration demonstrate the efficiency of this technique and its merit over the LMS-based techniques. Practical considerations have been considered and the proposed calibration has been applied on a 200 MS/s 40 nm CMOS split pipeline ADC to correct for the capacitor mismatch and the amplifier finite gain. The post-layout simulation results show a very fast calibration cycle, where the ADC achieves more than 11 ENOB in less than 1600 clock cycles.

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Section: Multistage Split Adc Calibration:operation and Analysismentioning

confidence: 99%

Section: Table I Calibration Time Comparison With Prior Artmentioning

confidence: 99%