Design Considerations of the Gmicro/100

Tomisawa, O.; Yoshida, Toyohiko; Matsuo, M.; Shimizu, Toshihisa; Enomoto, Tatsuya

doi:10.1007/978-4-431-68069-7_19

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1988

1989

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Cited by 4 publications

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“…The GMI-CR0/100 is designed as a small personal workstation CPU, an embedded system controller, and a core processor of application specific chips (ASIC's). It has 5-stage instruction pipeline scheme with a branch prediction mechanism and a branch target cache, and achieves two clock cycle execution of simple instructions, such as move, arithmetic and branch instructions [3], [4]. The G M I C R O /~~~ has high-level instructions such as those of bit-map manipulation.…”

Section: Introductionmentioning

confidence: 99%

A 32-bit microprocessor with high performance bit-map manipulation instructions

Shimizu

Iwata

Saito

et al.

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors

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The GMICRO/~OO, a 32-bit microprocessor based on the TRON architecture specification, has high performance bit-map manipulation instructions. The bit-map instructions are implemented by pipelining micro-operations and achieve optimum use of the memory bus in the execution. The bit-map instructions are 2 t o 3 times faster than repeating move instruction by the software. Microprogram development tools for the G M I C R O /~~~ design are also described in this paper.

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Section: Introductionmentioning

confidence: 99%