Design, Fabrication and Characterization of Single-Crystalline Graphene gNEMS ESD Switches for Future ICs

et al. 2022

Nanomaterials

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As the demands for improved performance of integrated circuit (IC) chips continue to increase, while technology scaling driven by Moore’s law is becoming extremely challenging, if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based complementary metal-oxide-semiconductor (CMOS) chips. The underlying basis for using HI technologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control, and actuation, which are required to facilitate comprehensive human–world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within acceptable design constraints, including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits, and system architectures, making it practically impossible to provide one single comprehensive review of everything in the field in one paper. This article chooses to offer a topical overview of selected HI structures that have been validated in CMOS platforms, including a stacked-via vertical magnetic-cored inductor structure in CMOSs, a metal wall structure in the back end of line (BEOL) of CMOSs to suppress global flying noises, an above-IC graphene nano-electromechanical system (NEMS) switch and nano-crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects.

Section: Graphene Nems Esd-protection Structurementioning

confidence: 99%

“… Measurement comparison of gNEMS devices made in single-crystal and polycrystal graphene films: ( a ) Raman spectrum, ( b ) DC sweeping test, and ( c ) TLP test [ 44 ]. …”

Section: Figurementioning

confidence: 99%

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Selective Overview of 3D Heterogeneity in CMOS

et al. 2022

Nanomaterials

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“…Fig. 1 illustrates the gNEMS ESD switch structure and its CMOS-compatible fabrication flow [8]. Briefly, it starts with a heavily P-doped Si wafer (bottom electrode).…”

Section: Graphene Esd Switch Fabricationmentioning

confidence: 99%

Investigating Graphene gNEMS ESD Switch for Design Optimization

IEEE J. Electron Devices Soc.

et al. 2021

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Traditional in-Silicon PN-junction-based on-chip electrostatic discharge (ESD) protection structures have inherent ESD-induced design overhead problems, including parasitic capacitance, leakage and Si area consumption. A potential solution to the ESD design overhead challenge is to use a non-conventional above-Si graphene-based nano-electrical mechanical system (gNEMS) transient switch structure to protect integrated circuits (ICs) against ESD failures. This paper reports investigation of materials and device structural impacts on gNEMS ESD protection structures. Transmission-line pulse (TLP) testing confirms that single-crystalline graphene gNEMS switch achieves a record high ESD currenthandling capability of J t2 ∼1.03×10 9 A/cm 2 , at least four times higher than J t2 ∼0.24×10 9 A/cm 2 for its poly-crystalline graphene counterpart. Transient 3D finite element method (FEM) simulation reveals that both device dimensions and shapes of the suspended graphene membranes can substantially affect gNEMS ESD discharging characteristics. The discovery offers guidelines for design optimization of gNEMS ESD switch structures.

“…The new internal-distributed CDM ESD protection method can be realized in some novel ways for added benefits. Traditionally, on-chip ESD protection utilizes large co-planar ESD protection structures in a side-by-side manner, i.e., inplane layout design with the core IC circuitry, which causes substantial ESD-induced design overhead (i.e., ESD-induced parasitic capacitance, leakage, and noises, as well as Si area consumed by large ESD protection devices and IC layout difficulty) [1,2,9]. In general, higher ESD protection robustness makes the ESD design overhead problem even worse.…”

Section: Interposer and Tsv-based Internal-distributed Esd Protectionmentioning

confidence: 99%

Non-Pad-Based in Situ In-Operando CDM ESD Protection Using Internally Distributed Network

IEEE J. Electron Devices Soc.

et al. 2021

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Charged device model (CDM) electrostatic discharge (ESD) protection is an emerging design challenge to ICs at advanced technology nodes. It was recently reported that the traditional pad-based CDM ESD protection methods are fundamentally faulty, which causes uncertainties in CDM ESD protection designs, testing and failure analysis. Re-thinking of onchip CDM ESD protection becomes imperative for complex ICs implemented in advanced technologies. This paper reports a disruptive CDM ESD protection method utilizing non-pad-based internally-distributed ESD protection network as a robust in situ in-operando CDM ESD protection solution. The proposed internal-distributed CDM ESD protection mesh network can be realized using interposer or through-silicon-via (TSV) ESD protection structures to achieve local 3D CDM ESD protection via heterogeneous integration. The new concept was validated using an internal-CDM-protected oscillator IC implemented in a foundry 45nm silicon-on-insulator (SOI) technology.