Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons

Yasunaga, Masahiro; Masuda, Naoyuki; Yagyu, Masayoshi; Asai, Masataro; Yamada, Manabu; Masaki, Akira

doi:10.1109/ijcnn.1990.137618

Cited by 47 publications

(11 citation statements)

References 4 publications

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“…In a conventional bus structure [24], [25], communication is a one-to-many broadcast and has low latency for small networks. However, a bus does not scale well with network size.…”

Section: A Two-layer Sparse Spiking Neural Networkmentioning

confidence: 99%

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Knag

Kim

Chen

et al. 2015

IEEE J. Solid-State Circuits

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Hardware-based computer vision accelerators will be an essential part of future mobile devices to meet the low power and real-time processing requirement. To realize a high energy efficiency and high throughput, the accelerator architecture can be massively parallelized and tailored to vision processing, which is an advantage over software-based solutions and general-purpose hardware. In this work, we present an ASIC that is designed to learn and extract features from images and videos. The ASIC contains 256 leaky integrate-and-fire neurons connected in a scalable two-layer network of 8 8 grids linked in a 4-stage ring. Sparse neuron activation and the relatively small grid keep the spike collision probability low to save access arbitration. The weight memory is divided into core memory and auxiliary memory, such that the auxiliary memory is only powered on for learning to save inference power. High-throughput inference is accomplished by the parallel operation of neurons. Efficient learning is implemented by passing parameter update messages, which is further simplified by an approximation technique. A 3.06 mm 65 nm CMOS ASIC test chip is designed to achieve a maximum inference throughput of 1.24Gpixel/s at 1.0 V and 310 MHz, and on-chip learning can be completed in seconds. To improve the power consumption and energy efficiency, core memory supply voltage can be reduced to 440 mV to take advantage of the error resilience of the algorithm, reducing the inference power to 6.67 mW for a 140 Mpixel/s throughput at 35 MHz.Index Terms-Feature extraction, hardware acceleration, neural network architecture, sparse coding, sparse and independent local network.

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“…In a conventional bus structure [24], [25], communication is a one-to-many broadcast and has low latency for small networks. However, a bus does not scale well with network size.…”

Section: A Two-layer Sparse Spiking Neural Networkmentioning

confidence: 99%

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Knag

Kim

Chen

et al. 2015

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

show abstract

“…Large sequential networks have been fabricated in electronics [6], however, if we are to meet the requirements for large networks and quick processing speeds we must implement cells which process concurrently. RAM-based neural networks [6] and wafer scale integration (WSI) of electronic systems have been investigated [7,8] and networks containing approximately 500 parallel processing neurons can be fabricated per wafer. Neural circuits can take advantage of WSI if they are fabricated in autonomous cells.…”

Section: Application Requirements and The Limits Of Electronic Technomentioning

confidence: 99%

Proposal for Stochastic Bit Stream Processing Using Optoelectronic Smart Pixels: A Neural Network Architectural Case Study

Hands

Peiffer

Thienpont

et al. 1997

Journal of Parallel and Distributed Computing

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“…Attempts began as early as the late 1980's [9,14]. This approach yields the greatest scope for architectural diversity as well as performance: different designs have used analogue [19] or digital [59] technology, hardwired [4] or configurable [57] architecture, continuousactivation [31] or spiking [43] signalling, coarse- [54] or fine-grained [8] parallelism. In recent years, however, interest has moved primarily towards processors for the simulation of spiking neural networks.…”

Section: Dedicated Neural Hardwarementioning

confidence: 99%

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Rast

Navaridas

Jin

et al. 2011

Int J Parallel Prog

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Neural networks present a fundamentally different model of computation from the conventional sequential digital model, for which conventional hardware is typically poorly matched. However, a combination of model and scalability limitations has meant that neither dedicated neural chips nor FPGA's have offered an entirely satisfactory solution. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. This parallel multiprocessor employs an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. Nonetheless, event handling, particularly packet servicing, requires careful and innovative design in order to avoid local processor congestion and possible deadlock. We explore the impact that spatial locality, temporal causality and burstiness of traffic have on network performance, using tunable, biologically similar synthetic traffic patterns. Having established the viability of the system for real-time operation, we use two exemplar neural models to illustrate how to implement efficient event-handling service routines that mitigate the problem of burstiness in the traffic. Extending work published in ACM Computing Frontiers 2010 with on-chip testing, simulation results indicate the viability of SpiNNaker for large-scale neural modelling, while emphasizing the need for effective burst management and network mapping. Ultimately, the goal is the creation of a library-based development system that can translate a high-level neural model from any description 123Int J Parallel Prog environment into an efficient SpiNNaker instantiation. The complete system represents a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.

show abstract

Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons

Cited by 47 publications

References 4 publications

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding

Proposal for Stochastic Bit Stream Processing Using Optoelectronic Smart Pixels: A Neural Network Architectural Case Study

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

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