Design Flow for High Switching Frequency and Large-Bandwidth Analog DC/DC Step-Down Converters for a Polar Transmitter

Abstract

International audienceSystem-on-chip requirements for energy management push both technology and design of voltage regulators to their limits. Integration constraints are added to high performance needs in terms of power efficiency and dynamic performance of the power converters. Switch-mode power supplies (SMPSs) are intended to supplant linear voltage regulators. This paper details a methodology to deal with different tradeoffs introduced by various specifications and constraints of embedded SMPSs. The design methodology is applied to the standard analog step-down SMPS architecture operating at very high switching frequency, and verified experimentally. The results are measured on test chips fabricated in standard 0.25-$mu$m BiCMOS technology, operating between 10 and 200 MHz, respectively, with a power efficiency up to 80% and a small-signal bandwidth of 1.2 and 15 MHz, respectively

Design of a Two-Phase Buck Converter With Fourth-Order Output Filter for Envelope Amplifiers of Limited Bandwidth

“…Buck converters are especially suitable for this approach due to the linear relationship that exists between the duty cycle and the output voltage at a constant input voltage if the converter is operating in the CCM. It should be noted that the use of a feedback loop, either of the EA output voltage [1]- [5], [8], [11], [29], [30], or of the RF envelope [6], [25], [28], guarantees a linear relationship between the control signal and the output voltage, even if the converters operates in the discontinuous conduction mode (DCM) or if the load is no longer constant. However, in this case the overall bandwidth is limited not only by the reactive elements of the power stage, but also by the dynamic response of the error amplifier, additional delays in the feedback loop, etc.…”

High temperature, high frequency micro-inductors for low power DC-DC converters

“…It is well known that passive components size depends on the switching frequency of the electrical waveforms. Sufficiently high switching frequency (>100 MHz) enables the decrease in the inductor size to few square millimeters [2]- [3]. It also allows increasing the dynamic response of the converter.…”

Analysis and design of switching amplifiers for smartphones

“…compared to other approaches such as the CDA-only [58][59][60][61][62][63][64] and the Class AB amplifieronly [81] architectures. In view of this, the hybrid CDA is ubiquitous as the choice of supply modulator for ET PAs and it is the architecture of interest in our designs.…”

“…Many supply modulators in ET PAs employ a hybrid topology (switching-cumlinear) [65][66][67][68][69][70][71][72][73][74][75][76][77][78]. This is because the hybrid CDA features higher power-efficiency compared to the Class AB amplifier-only topology [81], higher bandwidth and lower output ripple compared to the CDA-only topology [58][59][60][61][62][63][64] voltage of the input signal is 1.8V and the AC amplitude is 1.4V pp . In the low frequency range (<5MHz), is much higher than , and both and remain largely unchanged.…”

“…This is because the switching frequency of the CDA is required to be at least 5x wider than the bandwidth of the input signals to suppress the switching noise [11], and the ensuing high switching frequency results in significant large power loss [35]. Although some design techniques such as dual-switch [60], multi-phase [61], multi-level [62], have been proposed to reduce the required switching frequency of the CDA, the bandwidth of the state-of-the-art CDAs [58][59][60][61][62][63][64] is still relatively narrow (insufficient), which is limited to ~10MHz. In the contrast, the hybrid CDA comprising a wideband Class AB amplifier and a power-efficient CDA, depicted in Fig.…”