Design Flow for Hybrid CMOS/Memristor Systems—Part I: Modeling and Verification Steps

Abstract

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

A memristor fingerprinting and characterisation methodology for hardware security

“…It is worth noting that the presented methodology is appropriate for use both with standalone devices/arrays that can be evaluated with commercially available instrumentation tools 26 , 27 , as demonstrated in this paper, as well as with memristor/ReRAM technologies monolithically integrated onto CMOS. The latter would require both the physical integration of technologies as well as the integration of design kits and models 28 , 29 and is a potential avenue for future work. In such an integrated design, trade-offs must be made between convenience and the potential for an attacker to include additional hidden logic with reduced audibility.…”

Delta-Sigma Modulator Design Using a Memristive FIR DAC

“…In this design, we use the device model in [6], which was constructed based on the measured characteristics from the real fabricated Pt/Al2O3/TiO2/Pt stack memristors. The device can be programmed using voltage pulse trains to reach the This is the author's version of the work.…”

“…The simulation testbench to program and read the memristor is shown in Fig. 2(a), where the device was programmed with a train of 2V-amplitude and 100μs-wide pulses in accordance with the guidelines given in [6]. The verified resistance switching range of the memristor is 17.20kΩ to 55.63kΩ, as shown in Fig.…”

“…Besides, the memristors can be integrated with CMOS back-end-of-line process in 3D and thus do not occupy additional silicon area when they are placed on top of the CMOS circuitry [5]. Therefore, a memristive FIR DAC will have better reconfigurability, area, and power efficiency compared with the implementations using passive resistors [6]. The concept of memristive FIR was proposed in [3], and this work is the first demonstration of using memristive FIR for CTΔΣM design.…”

A CMOS-based Characterisation Platform for Emerging RRAM Technologies

“…Another challenge is the yield of the device and/or integration process [10], [11]. Being able to measure, model [12] and optimise this as per the application is vital in prolonging the life-span of the product.…”