Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

Yoneda, Tomokazu; Fujiwara, Hideo

doi:10.1007/978-1-4757-6527-4_8

Cited by 8 publications

(25 citation statements)

References 4 publications

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“…Transparency-based methods can be further classified into two types in terms of their properties of transparency: 1) single-cycle throughput transparency [20]- [23] and 2) multi-cycle throughput transparency [18], [19]. Single-cycle throughput transparency has two main advantages compared to multi-cycle throughput transparency: 1) short test application time and 2) ability to preserve timing information for test sequences.…”

Section: Introductionmentioning

confidence: 99%

“…Single-cycle throughput transparency has two main advantages compared to multi-cycle throughput transparency: 1) short test application time and 2) ability to preserve timing information for test sequences. In [20], a single-cycle throughput transparency-based TAM design method was proposed to minimize the area overhead of additional gate counts. The authors extended [20] so that it can handle test time and area overhead co-optimization problem in [21] and power constraints in [22].…”

Section: Introductionmentioning

confidence: 99%

“…In [20], a single-cycle throughput transparency-based TAM design method was proposed to minimize the area overhead of additional gate counts. The authors extended [20] so that it can handle test time and area overhead co-optimization problem in [21] and power constraints in [22]. [23] also proposed a single-cycle throughput transparency-based method to minimize the overhead of additional interconnect area.…”

Section: Introductionmentioning

confidence: 99%

“…[23] also proposed a single-cycle throughput transparency-based method to minimize the overhead of additional interconnect area. However, previous work [20]- [23] considered core-level transparency design problem and system-level TAM design problem separately. In other words, the authors first tackled only the design for transparency problem without considering the system level connectivity information.…”

Section: Introductionmentioning

confidence: 99%

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Design and Optimization of Transparency-Based TAM for SoC Test

Yoneda

Shuto

Ichihara

et al. 2010

IEICE Trans. Inf. & Syst.

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SUMMARYWe present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by considering test data flow for each core separately, (2) optimization of the cost for transparency as well as the cost for additional interconnect area simultaneously and (3) consideration of additional bypass paths. Therefore, the proposed ILP model can represent various problems including the same problem as the previous work and produce better results. Experimental results show the effectiveness and flexibility of the proposed method compared to the previous work.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design and Optimization of Transparency-Based TAM for SoC Test

Yoneda

Shuto

Ichihara

et al. 2010

IEICE Trans. Inf. & Syst.

Self Cite

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show abstract

“…Although core reuse increases the productivity, due to the growing transistor-to-pin ratio and the increasing number of embedded cores that are not directly accessible from the input/output (I/O) ports of the SOC, the manufacturing test is posing a design implementation problem. Various solutions for exploiting the SOC's architecture-specific information and using functional interconnect as test access mechanisms (TAMs), either at the core or system level, have been proposed [4], [5], [8], [22], [29], [31], [42]. Regardless of their potential benefits in the long term, unless implemented automatically using a reliable test tool flow, these architecture-specific design for test (DFT) methodologies do not provide reusability, scalability, or interoperability and may become the computational bottleneck in the test automation flow.…”

Section: Introductionmentioning

confidence: 99%

Modular and rapid testing of SOCs with unwrapped logic blocks

Nicolici

2005

IEEE Trans. VLSI Syst.

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Abstract-Extensive research has been carried out for test planning of core-based system-on-a-chip devices. Most of the prior work assumes that all of the embedded cores are wrapped for test purpose. However, some designs may contain user-defined logic or cores that cannot be wrapped due to area constraints or timing violations. This paper discusses how these unwrapped logic blocks can be tested rapidly by adapting the TestRail architecture, which uses only the test control mechanism and the test instructions available through the IEEE 1500 standard for embedded core test. A new test scheduling algorithm, which facilitates a concurrent test of both unwrapped logic blocks and IEEE 1500-wrapped cores, is proposed, and experiments show that it outperforms a previous approach when the available number of tester channels and/or the number of unwrapped logic blocks are small.

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Design for consecutive transparency method of RTL circuits

Yoneda

Fujiwara

2006

Syst. Comp. Jpn.

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SUMMARYIn this paper, the authors propose a design for a consecutive transparency method for modifying the design of cores embedded in a system-on-a-chip (SoC), where the cores are register transfer level (RTL) circuits, so that the circuits satisfy consecutive transparency requirements. Consecutive transparency of a core is a property that enables an arbitrary length sequence that is input from each input port to be propagated to the output side in consecutive clock cycles without changing the sequence values or an arbitrary length sequence that is output from each output port to be propagated from the input side in consecutive clock cycles by selecting a configuration (test mode). Therefore, when a consecutively transparent core is embedded in an SoC, that core can be used as a path for consecutive test access to other cores and interconnects within the SoC. For a consecutive test accessible SoC, even when arbitrary test sequences for arbitrary fault models are applied to cores and interconnects, assumed faults must be completely tested by using those sequences. The authors also show through experiments that the area overhead due to the proposed design for consecutive transparency method is lower than when consecutive transparency was implemented according to a bypass path from input to output by using only a multiplexer.

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Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores

Cited by 8 publications

References 4 publications

Design and Optimization of Transparency-Based TAM for SoC Test

Design and Optimization of Transparency-Based TAM for SoC Test

Modular and rapid testing of SOCs with unwrapped logic blocks

Design for consecutive transparency method of RTL circuits

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