Design-for-Debugging of application specific designs

Abstract

IntroductionIt is well-known that functional debugging usually dominates the cost of design development. Debugging is in particular a difficult activity when real-time full-custom ASIC designs are targeted, due to the strict timing constraints and a lack of flexibility during execution.We have four main objectives of the research presented in this paper: 1. to formalize an intuitive notion of ASIC debugging so that it can be treated as a design and CAD activity; 2. to identify key design and high level synthesis principles which support debugging; 3. to developed efficient high level synthesis algorithms for optimization problems related to ASIC debugging; and 4. to give an impetus for creation of design-for-debugging and synthesis-for-debugging methodologies.Debugging is a process of detecting, diagnosing, and correcting errors in the specification of an ASIC implementation. Error is any discrepancy between desired and realized behavior of the specification of the design. The debugging process can be divided into three phases [Ren89]. The first step is error detection, in which the designer discovers that a program (design) does not function correctly for a particular input. The second phase is error diagnosis in which the programmer/designer identifies the statement or the section of the code which is causing the incorrect behavior. The third step is error correction, in which the faulty section or the statement responsible for the observed fault is replaced by the corrected section.In the research presented in this paper, we concentrate on the error detection phase. Even when only this phase is considered there can be numerous different strategic approaches. However, it is widely accepted that providing simultaneous controllability and observability of as many as possible variables of the program under execution immensely facilitates the debugging process.Therefore, we will informally define the design-fordebugging problem in the following way. Given is an ASIC design. The design is fully specified: the control-data flow graph (CDFG) of the computation, timing constraints in terms of the available number of control steps, and the schedule and assignment of each operation, variable and constant, and data transfer are given. Furthermore, a set of desired controllable debug variables (write variables) and observable debug variables (read variables) is specified by the user. The goals of a design-for-debugging (DfD) technique is to modify design such that the set of desired debug variables are made controllable/observable, satisfying given timing constraints, while adding a minimal additional hardware.The key constraint of the DfD is that functionality of the design should not be altered in any way, except when requested by the user when debugging variables should be altered by the user provided values. The key idea is to use available I/O pins for reading and writing debug variables in control steps when they are not used by the design variables.We conclude this section by pointing out key differences b...

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“…In addition to a programmability gap between FPGAs and CPUs, there is a debuggability gap that has received far less attention. The programmability of FPGAs has improved over the years, but they are not debuggable by default (Potkonjak et al 1995). FPGAs provide no visibility into the running program, and their standard tooling provides very limited support for this.…”

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“…Quickturn, MentorGraphics. Potkonjak et al 8 propose a design for debugging technique. Their technique focuses only on the error diagnosis phase.…”

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“…For example, they can be used to facilitate debugging [31] and engineering change during the design phase or testing once the chip is manufactured [10].…”