Design for manufacturability: IC layout density optimization by minimum-variance method

Abstract

Design for manufacturing is important in the deep-submicron regime. Increasing integrated circuit (IC) layout uniformity by adding non-functional metal lines in the empty area, so-called dummy feature filling, is an efficient and effective way to reduce pattern-induced topography variation in the chemicalmechanical polishing (CMP) process of IC fabrication. Most existing dummy feature filling methods for IC layout density optimization seek to minimize the effective density range ( H À L ), where H is the highest and L is the lowest effective density calculated by CMP models. This objective function is not suitable for designs with a wide pattern-density range. First, the minimum value of the effective density range ( H À L ) may be fixed because L or H is constrained by chip design and, second, all effective densities will be brought as close as possible to H , making the final effective density distribution inappropriate for process recipe development. Here, we propose a new objective functionminimize the overall effective density variance 2 d . This overcomes the limitations of existing minimumrange approaches. Because linear programming methods for solving minimum-variance problems are time consuming, a mean-based heuristic method is proposed with reduced computational cost. Experiments on two large-sized IC designs showed that the proposed minimum-variance dummy filling method not only achieved the minimum effective density range, but also minimized the effective density variance of the designed layouts.