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A methodology is proposed to characterize the electrical performance of model-based dummy feature insertion in Cu interconnect. Two types of test structures were designed to explore the electrical performance discrepancy between the rule-based and model-based dummy feature insertion. The sheet resistance dependency on design rule is characterized at the various density conditions. 2-D field solver extracts the parasitic capacitance caused by dummy feature insertion A model-based dummy feature insertion algorithm using randomized shapes is proposed to assist the uniformity control of Cu CMP and MITBEMATECH 854 AZ test vehicle is used to demonstrate the feasibility of the proposed algorithm.

Wafer Bin Maps (WBMs) are important for yield improvement to trace root causes. The characteristic of WBMs patterns are formed by processes, so process engineers can collect clues from the patterns and correlate them with speciJic processes. and this can save much time and eforts in finding the root causes. However, the existing learning algorithms have the main shortage of product dependency. For this reason, this work adopted a supervised learning methodology to develop an on-line WBMs pattern recognition system that maps WBMs into 70x70 binary images to salve this issue. Furthermore, this work also proposed a learning scheme to recognize repeating failures that are usually viewed as random pattern in the existing approaches.

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