Design for reliability: Thermo-mechanical analyses of stress in Through Silicon Via

Abstract

Increasing demand, regarding to advanced 3D packages and high performance applications, accelerates the development of 3D silicon integrated circuit, with the aim to miniaturize and reduce cost. The study of the reliability of the through silicon via and of most critical areas for the emergence of failure remains a major concern. This paper deals with the variation of stress and strain induced in a through silicon via. It exhibits different recommendations to improve the reliability through a screening of influential parameters. These studies are focused on a single Through Silicon Via (TSV).The stress and strain induced in a TSV depends on different materials and geometrical parameters. Simulation results of accumulated stress and plastic strain show that the interface between copper and silicon is an indicator for a potential failure such as delamination and die cracking. The stress in the TSV also depends on the variation of copper filling, the size of holes and the thickness of wafers. Increasing via diameter increases the stress in the TSV and the effect of thermal expansion mismatch between copper, silicon and silica.

Simulation of Cu pumping during TSV fabrication

“…According to the simulation results, the magnitude of radial stress after sintering on top of TSV is tensile, and the Silicon next to the TS V is in compression. This is in agreement with other publications (for example [7]). Since other papers assume a stress free temperature (ex.…”

“…The results of previous models[5][6][7][8] agree that the shear stress at the interface is the highest. For our model to be able to cope with the large variation of stresses and strains at the interface, the mesh size for those locations are made smaller than in the rest of the model.As shown in figure 3, the simulation is divided into three successive sequences to cover the processes such as CMP where part of the Cu (i.e.…”

“…For example in [5] TSV stress fields have been investigated as a function of TSV depth and in [6] it is shown that thermal cycling increases thermo-mechanical stresses and affect BEOL metal layers. A statistical approach in connection with finite element modeling has been employed in [7] to analyze the effect of various parameters such as TSV diameter, substrate thickness, Young modulus and yield stress of Cu on stress and plastic strain. In [8], an axisymmetric model is used and the effect on the carrier mobility has been studied by analyzing stresses induced by Cu in Silicon.…”

Investigation of durability of TSV interconnect by numerical thermal fatigue analysis

“…In TSV technology, however, the driving failure may be the TSV interconnects failures. 2,3 Copper is widely used for the TSV filling material because of its low electrical resistivity. However, the coefficient of thermal expansion (CTE) of copper (~17.5×10 -6 /°C) is much higher than that of silicon (~2.5×10 -6 /°C).…”

Simulation of μ-Bump and TSV in 3-D Integration

“…Local temperature and temperature gradient distributions as well as local mechanical stress can be achieved by the simulations. In the past the prediction of local weak spots in interconnect contacts as well as TSVs and solders bumps by finite element simulations were described as a helpful procedure [1,2]. The birth-death method was used to replicate the manufacturing steps.…”