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Increasing demand, regarding to advanced 3D packages and high performance applications, accelerates the development of 3D silicon integrated circuit, with the aim to miniaturize and reduce cost. The study of the reliability of the through silicon via and of most critical areas for the emergence of failure remains a major concern. This paper deals with the variation of stress and strain induced in a through silicon via. It exhibits different recommendations to improve the reliability through a screening of influential parameters. These studies are focused on a single Through Silicon Via (TSV).The stress and strain induced in a TSV depends on different materials and geometrical parameters. Simulation results of accumulated stress and plastic strain show that the interface between copper and silicon is an indicator for a potential failure such as delamination and die cracking. The stress in the TSV also depends on the variation of copper filling, the size of holes and the thickness of wafers. Increasing via diameter increases the stress in the TSV and the effect of thermal expansion mismatch between copper, silicon and silica.

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