1996
DOI: 10.1049/ip-cds:19960956
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Design-for-test (DfT) study on a current mode DAC

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Cited by 9 publications
(2 citation statements)
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“…The digital module includes combinational logic cells and sequential memory registers. The BICS is placed between the CUT ground and the ground package pin [13].…”
Section: Fig 4 Catastrophic Transistor Fault Modelmentioning
confidence: 99%
“…The digital module includes combinational logic cells and sequential memory registers. The BICS is placed between the CUT ground and the ground package pin [13].…”
Section: Fig 4 Catastrophic Transistor Fault Modelmentioning
confidence: 99%
“…Therefore, several fault-based BIST schemes have been proposed as an alternative testing method, targeted here for the detection of manufacturing defects. In [2], a fault-based testing strategy was investigated by observing the power supply current in the digital section of the DAC-Under-Test (DUT), and the voltage and bias current in the analog section. However, it is not suitable for self-test.…”
mentioning
confidence: 99%