Design for testability of a 32-bit TRON microprocessor

Nozuyama, Y.; Nishimura, A.; Iwamura, Jun

doi:10.1016/0141-9331(89)90030-6

Cited by 2 publications

(2 citation statements)

References 8 publications

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“…[hlicroBIST] A microBIST with a masked microinstruction scheme was introduced first into the TX1 [5], which effectively reduces the number of words of test microprograms for almost all microinstruction controlled macroblocks, which are stored in a microROM with microprograms for normal operation. Figure 4a shows the block diagram of a microBIST with the scheme.…”

Section: Bistmentioning

confidence: 99%

“…It has 350k transistors and performs 10-12 VAXh,IIPS at 25MHz of internal clock frequency. Into the TX2, a combination of powerful BIST(Bui1t-In Self Test)s and parallel scan design, is implemented for manufacturing test, in a more sophisticated manner than into the TX1 [5]. The fact being made account of, that the TX2 is used as a core processor of ASSP(App1ication Specific Standard Product)s, for much shortening test time, every effort was made to implement powerful BISTs which achieve 100% functional coverage of ROM, RAM and PLA, and more than 80% coverage of single stuck-at faults of the remaining part of the TX2, with a moderate (4 5%) area overhead.…”

Section: Introductionmentioning

confidence: 99%

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A 32-bit microprocessor with efficient testable designs, the TX2

Nozuyama¹,

Mitani²,

Fukumoto³

et al.

Proceedings of the 11th TRON Project International Symposium

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A 32-bit microprocessor, the T X 2 , with efficien.2 testable designs, has been developed. For manufacturing test, a combinaiion of powerful BISTs and parallel scan design is implemented. The BISTs achieze 100% funciional coverage for ROM, RAM and P L A and 78%: coverage of single stuck-at faults of the remaining pari of ihe T X 2 including redundant faults. Scan test vectors obtained b y A T P G have enhanced the corerage i o 84%. Total lest time is less ihan 2 seconds. There are also a few circuitry for efficient design zerification. Moreover, f o r higher test quality, Idd,q test is implemented. Total area overhead is 6.9%

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Section: Bistmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 32-bit microprocessor with efficient testable designs, the TX2

Nozuyama¹,

Mitani²,

Fukumoto³

et al.

Proceedings of the 11th TRON Project International Symposium

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A built‐in self‐test structure for arithmetic execution units of VLSIs

Ikenaga

Takahashi

1995

Electron Comm Jpn Pt II

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This paper proposes advanced built‐in self‐test (BIST) structures: a bit‐distributed pattern generator (BDPG) and a multistage space compressor (MSSC) for arithmetic execution units of VLSIs. By focusing on the regularity of the arithmetic execution units, the required area overhead of the BIST circuits is less than that of conventional ones. The experimental result shows that these structures can reduce almost 60 percent of the hardware overhead of conventional BIST circuits while maintaining high‐fault coverage. These BIST configurations will make a significant contribution to test cost reduction for the performance‐orientation digital LSIs, especially digital signal processor LSIs.

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Design for testability of a 32-bit TRON microprocessor

Cited by 2 publications

References 8 publications

A 32-bit microprocessor with efficient testable designs, the TX2

A 32-bit microprocessor with efficient testable designs, the TX2

A built‐in self‐test structure for arithmetic execution units of VLSIs

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