Design for Verification in System-level Models and RTL

Mathur,; Krishnaswamy,

doi:10.1109/dac.2007.375151

Cited by 5 publications

(4 citation statements)

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“…Ref. [19] discusses general challenges in combining a system-level model with a RTL model in a co-simulation setting from the verification perspective. [20] proposes a co-simulation environment for SystemC and Verilog modules by integrating both simulation kernels and using custom channels on top of the Verilog Procedural Interface for communication.…”

Section: Related Workmentioning

confidence: 99%

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Ahmadi-Pour,

Logemann,

Herdt

et al. 2023

Chips

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In this paper, we propose a Virtual Prototype (VP) driven verification methodology for Hardware (HW) peripherals. In particular, we combine two approaches that complement each other and use the VP as a readily available reference model: We use (A) Coverage-Guided Fuzzing (CGF) which enables comprehensive verification at the unit-level of the Register-Transfer Level (RTL) HW peripheral with a Transaction Level Modeling (TLM) reference, and (B) an application-driven co-simulation-based approach that enables verification of the HW peripheral at the system-level. As a case-study, we utilize a RISC-V Platform Level Interrupt Controller (PLIC) as HW peripheral and use an abstract TLM PLIC implementation from the open source RISC-V VP as the reference model. In our experiments we find three behavioral mismatches and discuss the observation of these, as well as non-functional timing behavior mismatches, that were found through the proposed synergistic approach. Furthermore, we provide a discussion and considerations on the RTL/TLM Transactors, as they embody one keystone in cross-level methods. As the different approaches uncover different mismatches in our case-study (e.g., behavioral mismatches and timing mismatches), we conclude a synergy between the methods to aid in verification efforts.

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Section: Related Workmentioning

confidence: 99%

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Ahmadi-Pour,

Logemann,

Herdt

et al. 2023

Chips

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“…The following guidelines [4] should be followed by design teams to effectively use SEC or other simulationbased techniques for keeping SLMs and RTL functionally equivalent:…”

Section: Guidelines For Effective Slm Versus Rtl Verificationmentioning

confidence: 99%

Leveraging sequential equivalence checking to enable system-level to RTL flows

Urard¹,

Maalej²,

Guizzetti³

et al. 2008

Proceedings of the 45th Annual Design Automation Conference

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It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often the case that by the end of a design project, multiple C models exist for different uses. Since a lot of time is invested in ensuring the functional correctness of these models via their use in system-level simulations, they often become "golden" functional reference models. Design teams are moving towards leveraging these system-level models to reduce the time needed for design and verification of RTL. On the design side, the use of high-level synthesis tools to synthesize RTL from C/C++ models is gaining ground for certain classes of blocks within a design. On the verification front, temporal differences at interfaces and in internal states between system-level models and RTL prevent the use of combinational equivalence checkers. This paper focuses on the use of sequential equivalence checking to verify functional equivalence between system-level models and RTL and describes the challenges and vale of using it in system-level to RTL flows. IntroductionC/C++ and SystemC models are created by SoC design teams to serve different purposes during design including architectural exploration, software prototyping, supplying customers with executable prototypes, and verification of RTL models.In this paper we will refer to these models as system-level models (SLM). Since these tasks to which the models are put differ widely in purpose, the SLMs created for each of these can vary in abstraction level across the axes of functional accuracy and level of detail in modeling communication.With a significant part of the overall design cycle being consumed in developing and validating SLMs, it is imperative for design teams to leverage the effort spent in designing and verifying SLMs to simplify the design and verification of RTL. On the design side, high-level synthesis (HLS) flows are starting to get adopted to synthesize RTL from SLMs for certain types of blocks in designs. HLS tools allow for automatic generation of RTL, thus moving the bulk of the design effort to the SLM level. HLS tools also allow the exploration of different micro-architectures since the creation of RTLs with different latency/throughputs and hence different control/computation structures is now much easier. However, the use of HLS creates the need for an automated flow to ensure the correctness of the synthesizable SLM that is the input to HLS and the RTL generated from HLS. Even if no HLS tools are used in RTL creation, design teams want to keep the SLM and RTL functionally equivalent.Traditionally, simulation of the SLM and RTL using consistent input vectors and comparison of the output vectors using an intelligent "diff" or co-simulation of the SLM and RTL have been the vehicles of choice to verify equivalence between SLMs and RTL. However, simulation-based approaches require significant effort in developing testbenches and yield partial coveragepotentially missing out on ...

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“…Mathur et al proposed to use system-level models to assist the verification of the RTL code [9]. However, their methods cannot be applied when system-level models are unavailable.…”

Section: Introductionmentioning

confidence: 98%

Improving design verifiability by early RTL coverability analysis

Chang

Jiang

et al. 2012

Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMCODE2012)

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Achieving high coverage is an important goal in design verification. Fixing coverability problems found at the verification stage, however, can require tremendous effort. To address this problem, we propose a flow for analyzing code and variable-toggle coverability at the early-RTL block-level stage. In addition, we devise a novel technique to analyze the coverability problems so that engineers can resolve the issues more efficiently. By identifying coverability problems at early RTL design stages, design verifiability can be improved, thus reducing the effort required at the verification phase.

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Design for Verification in System-level Models and RTL

Cited by 5 publications

References 0 publications

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Synergistic Verification of Hardware Peripherals through Virtual Prototype Aided Cross-Level Methodology Leveraging Coverage-Guided Fuzzing and Co-Simulation

Leveraging sequential equivalence checking to enable system-level to RTL flows

Improving design verifiability by early RTL coverability analysis

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