Design Guideline of 2.5D Package with Emphasis on Warpage Control and Thermal Management

Hong, Ji‐Sun; Choi, Kyoungsei; Oh, Dan; Sb, Park; Shao, Shuyan; Wang, Huayan; Niu, Yuling; Pham, Van Lai

doi:10.1109/ectc.2018.00108

Cited by 35 publications

(7 citation statements)

References 3 publications

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“…First, high- performance chips are laterally placed close to each other while their temperature-sensitivity and mechanical-reliability metrics are different. This is a common scenario in 2.5D package platforms [28,46,79,[82][83][84][85][86][87][88][89][90][91][92][93]. Second, high-performance chips are vertically stacked, while the thermal resistance increases with the number of stacked chips.…”

Section: Thermal Management Challenges In Heterogeneousmentioning

confidence: 99%

“…This requires effective cooling very close to the heat source. However, some of the 2.5D packages have various layers, such as TIM and heat slug layers, between the heat source and the heat sink for reliability concerns at the board level [83,85,89,92]. When the heat sink has a rough contact surface and the 2.5D package has a large thermally induced or assembly warpage, the possibility of the active device cracking and failure increases after the heat sink is attached.…”

Section: Thermal Management Challenges Due To Multichipmentioning

confidence: 99%

“…High-thermal conductivity and low BLT are preferred for thermal management [113][114][115]. In 2.5D package platforms, TIMs are typically used on ASIC (application-specific) and HBM [85]. ASIC and HBM have different thermomechanical properties, because ASICs are made of a single chip, and HBMs are made of several chips with multilevel vertical stacks.…”

Section: Thermal Interface Materialsmentioning

confidence: 99%

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Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Kim

Ren

Yuksel³

et al. 2020

Journal of Electronic Packaging

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Thermal metamaterials exhibit thermal properties that do not exist in nature but can be rationally designed to offer unique capabilities of controlling heat transfer. Recent advances have demonstrated successful manipulation of conductive heat transfer and led to novel heat guiding structures such as thermal cloaks, concentrators, etc. These advances imply new opportunities to guide heat transfer in complex systems and new packaging approaches as related to thermal management of electronics. Such aspects are important, as trends of electronics packaging toward higher power, higher density, and 2.5D/3D integration are making thermal management even more challenging. While conventional cooling solutions based on large thermal-conductivity materials as well as heat pipes and heat exchangers may dissipate the heat from a source to a sink in a uniform manner, thermal metamaterials could help dissipate the heat in a deterministic manner and avoid thermal crosstalk and local hot spots. This paper reviews recent advances of thermal metamaterials that are potentially relevant to electronics packaging. While providing an overview of the state-of-the-art and critical 2.5D/3D-integrated packaging challenges, this paper also discusses the implications of thermal metamaterials for the future of electronic packaging thermal management. Thermal metamaterials could provide a solution to nontrivial thermal management challenges. Future research will need to take on the new challenges in implementing the thermal metamaterial designs in high-performance heterogeneous packages to continue to advance the state-of-the-art in electronics packaging.

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Section: Thermal Management Challenges In Heterogeneousmentioning

confidence: 99%

Section: Thermal Management Challenges Due To Multichipmentioning

confidence: 99%

Section: Thermal Interface Materialsmentioning

confidence: 99%

See 1 more Smart Citation

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Kim

Ren

Yuksel³

et al. 2020

Journal of Electronic Packaging

Self Cite

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“…Recently, Samsung [141,142] proposed using chip-last or RDLfirst FOWLP to eliminate the TSV-interposer as shown in Fig. 38.…”

Section: Opportunities For Fan-out Wafer-level Packagingmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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“…Over the years, the thickness of electronic devices, such as smartphones and tablet PCs, has continually decreased according to consumer needs. As such, the semiconductor packages used in electronic devices are also being developed to be thinner and more highly integrated in performance. − Accordingly, various packages, such as system in package (SiP), package on package (PoP), and multi-chip package (MCP), have been developed. , One of the important roles of the semiconductor package is to protect the silicon chips and wires from mechanical and thermal shocks by encapsulating them with plastic molding technology and to effectively dissipate the heat generated during chip driving. Semiconductor plastic encapsulation technology uses an epoxy molding compound (EMC), which is over 80 wt % silica filler content polymeric composite material consisting of silica, epoxy resin, hardener, and other additives. , EMC is liquified and injected into the cavity with a plunger or placed directly into the cavity and liquified before the workpiece is immersed in it for resin molding and then cured by the manufacturer’s recommended cure cycles.…”

Section: Introductionmentioning

confidence: 99%

Electronic Packaging Enhancement Engineered by Reducing the Bonding Temperature via Modified Cure Cycles

Park

Kim

et al. 2023

ACS Appl. Mater. Interfaces

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Semiconductor packaging continues to reduce in thickness following the overall thinning of electronic devices such as smartphones and tablets. As the package becomes thinner, the warpage of the semiconductor package becomes more important due to the reduced bending stiffness and driven by thermal residual stresses and thermal expansion mismatch during the epoxy molding compound (EMC) curing to create the package. To address this packaging reliability issue, in this study, we developed a modified cure cycle that adds a rapid cooling step to the conventional cure cycle (CCC) to enhance the reliability of the EMC molded to a copper substrate (EMC/Cu bi-layer package) by lowering the bonding temperature of the EMC/Cu bi-layer package. Modeling of the package via Timoshenko theory including effective cure shrinkage allowed the rapid cooling step to be quantified and confirmed via experiments. The modified cure cycle resulted in a 26% reduction in residual strain, a 27% reduction in curvature, and a 40% increase in peel strength compared to the CCC, suggesting that this is an effective new method for managing warping effects in such packaged structures.

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Design Guideline of 2.5D Package with Emphasis on Warpage Control and Thermal Management

Cited by 35 publications

References 3 publications

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Recent Advances in Thermal Metamaterials and Their Future Applications for Electronics Packaging

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Electronic Packaging Enhancement Engineered by Reducing the Bonding Temperature via Modified Cure Cycles

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