Design Guidelines for Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs)

Lee, Jang Woo; Choi, Woo Young

doi:10.1109/access.2020.2985125

Cited by 21 publications

(16 citation statements)

References 26 publications

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“…Fermi-Dirac statistics, doping concentration dependent mobility, Shockley-Read-Hall (SRH) recombination, and modified local density approximation (MLDA) models were used to calculate and extract the electrical characteristics of TFETs in the simulation. For an accurate calculation of band-to-band tunneling (BTBT), a dynamic non-local BTBT model was applied with theoretically calculated parameters [46] generally used in recent TFET research [47][48][49].…”

Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure

Kım

Kim

et al. 2020

Applied Sciences

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Metal gate technology is one of the most important methods used to increase the low on-current of tunnel field-effect transistors (TFETs). However, metal gates have different work-functions for each grain during the deposition process, resulting in work-function variation (WFV) effects, which means that the electrical characteristics vary from device to device. The WFV of a planar TFET, double-gate (DG) TFET, and electron-hole bilayer TFET (EHBTFET) were examined by technology computer-aided design (TCAD) simulations to analyze the influences of device structure and to find strategies for suppressing the WFV effects in TFET. Comparing the WFV effects through the turn-on voltage (Vturn-on) distribution, the planar TFET showed the largest standard deviation (σVturn-on) of 20.1 mV, and it was reduced by −26.4% for the DG TFET and −80.1% for the EHBTFET. Based on the analyses regarding metal grain distribution and energy band diagrams, the WFV of TFETs was determined by the number of metal grains involved in the tunneling current. Therefore, the EHBTFET, which can determine the tunneling current by all of the metal grains where the main gate and the sub gate overlap, is considered to be a promising structure that can reduce the WFV effect of TFETs.

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Section: Device Structure and Simulation Methodsmentioning

confidence: 99%

Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure

Kım

Kim

et al. 2020

Applied Sciences

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“…It can have the sub-60 mV/dec steeper SS by using interband tunneling as a carrier injection mechanism as well as the larger tunneling current by extending the tunneling area compared to conventional TFETs. In spite of these advantages, it is hard to obtain the abrupt on/off transition in the gate-normal TFETs because the occurrence of the corner tunneling at the edge of the source region underneath the gate degrades SS and even causes the drain current hump [21].…”

Section: Introductionmentioning

confidence: 99%

Steep Switching Characteristics of L-Shaped Tunnel FET With Doping Engineering

Kim

Kwon

2021

IEEE J. Electron Devices Soc.

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In this work, a L-shaped tunnel FET (TFET), which has the dominant tunneling current in the normal direction to the gate, is introduced with the doping engineering and its electrical characteristics are analyzed using TCAD device simulations. The proposed L-shaped TFET has the pocket doping (p + -doping for ntype operations) underlying the gate, which can suppress the corner tunneling generated near the source edge by the electricfield crowding. Thus, the on/off transition is significantly improved since the corner tunneling is the main cause of the degradation of the switching characteristics. To maximize the performance enhancement, the concentration of the pocket doping (NPOC) is optimized. As a result, the averaged subthreshold swing (SSAVE) gets reduced from 60 to 26 mV/dec and the on-current (ION) becomes ~ 2.0 times increased as compared to the conventional Lshaped TFETs. Moreover, it is confirmed that the pocket doping effectively suppresses the corner tunneling without the on-current reduction even in the extremely scaled gate length (LG) device.

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“…Therefore, counter‐doped line horizontal pockets (HPs) below gates were reported, which reduced the high onset voltage requirements as well as the gate variability effects 3 . Since then, line TFETs based on ultra‐thin pockets have gained popularity 4‐20 …”

Section: Introductionmentioning

confidence: 99%

“…However, the formation of overlapped pockets on channel is still subject to precise channel etch steps. Recently, inverted L‐shaped pockets, 19 GHD TFET incorporating a source channel epi‐layer line pocket, 17 and fully extended source to drain epi‐layer pocket have also been reported 21 . At such scaled nano‐dimensions, especially for heterojunction designs, studies on the design reliability aspects become essential; 2,6,16,17,22,23 however, not much work has been that in that respect.…”

Section: Introductionmentioning

confidence: 99%

“…Recently, inverted L‐shaped pockets, 19 GHD TFET incorporating a source channel epi‐layer line pocket, 17 and fully extended source to drain epi‐layer pocket have also been reported 21 . At such scaled nano‐dimensions, especially for heterojunction designs, studies on the design reliability aspects become essential; 2,6,16,17,22,23 however, not much work has been that in that respect. Further, designs particularly based on SiGe/Si line tunneling heterojunctions 7‐14 that have been actually demonstrated till now adhere to fabricated Si pockets lying in the range of 6‐7 nm, 7,10 with the very recent gate‐normal TFET comprising a relaxed ~10 nm line pocket 9 .…”

Section: Introductionmentioning

confidence: 99%

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Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

Ashita

Loan

Alkhammash

et al. 2021

Int J Numerical Modelling

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In this work, we propose and investigate a new pocket‐based Si0.55Ge0.45/Si gate normal tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with and without a heterogeneous dielectric (HD) gate oxide. Miller capacitance is significantly reduced with the GSLP design, which is further improved by the HD gate oxide leading to full overshoot/undershoot suppression capability in transient response. Further, a steep switching with more than one order improvement in ON current is achieved when compared to state‐of‐the‐art line pocket designs. As a result, an ~98.8% and ~88% improved intrinsic delay (CGGVDD/ION) is achieved in comparison to dual line pocket and non‐pocketed designs, respectively. Additionally, an improved worst‐case trap‐charge tolerance, reduced pocket‐width‐induced fluctuations, and excellent immunity to gate misalignment‐induced fluctuations are achievable just by replacing the gate‐aligned parallel‐line pockets with a vertically aligned single‐lateral pocket (LP) improving the design reliability. A Ge/Si HD‐GSLP TFET design further offers stable ON currents with SS < 60 mV/dec over a feasible range of pocket widths between ~6 and 8 nm at VDS = VGS = 0.7 V.

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Design Guidelines for Gate-Normal Hetero-Gate-Dielectric (GHG) Tunnel Field-Effect Transistors (TFETs)

Cited by 21 publications

References 26 publications

Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure

Analysis of Work-Function Variation Effects in a Tunnel Field-Effect Transistor Depending on the Device Structure

Steep Switching Characteristics of L-Shaped Tunnel FET With Doping Engineering

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

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