In this study, vertical tunnel FET-based ternary CMOS (T-CMOS) is introduced and its electrical characteristics are investigated using TCAD device and mixed-mode simulations with experimentally calibrated tunneling parameters. This new T-CMOS utilizes two different types of tunneling currents to form three different output voltage states: (1) source-to-drain tunneling current; and (2) conventional source-to-channel tunneling current. To form a half supply voltage (V DD) output voltage during the inverter operation, the n-/p-type devices of the proposed T-CMOS are designed to have constant source-to-drain tunneling current regardless of gate voltage (V GS) by using nitride spacer between gate and drain. Also, typical binary inverter operation is performed using the source-to-channel tunneling. In voltage transfer characteristics (VTC), it is confirmed that there is the clear half V DD state after matching the tunneling currents of the n-/p-type devices. It is revealed that the stable half V DD state cannot be achievable if the currents are mismatched by gate workfunction, gate dielectric thickness, and interface trap variations, implying that the current matching between n-/p-type devices is crucial to obtain stable ternary operations. INDEX TERMS Band-to-band tunneling (BTBT), vertical tunnel field-effect transistor (vertical tunnel FET), ternary inverter, subthreshold swing (SS), ternary CMOS (T-CMOS), line tunneling.

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In this work, a L-shaped tunnel FET (TFET), which has the dominant tunneling current in the normal direction to the gate, is introduced with the doping engineering and its electrical characteristics are analyzed using TCAD device simulations. The proposed L-shaped TFET has the pocket doping (p + -doping for ntype operations) underlying the gate, which can suppress the corner tunneling generated near the source edge by the electricfield crowding. Thus, the on/off transition is significantly improved since the corner tunneling is the main cause of the degradation of the switching characteristics. To maximize the performance enhancement, the concentration of the pocket doping (NPOC) is optimized. As a result, the averaged subthreshold swing (SSAVE) gets reduced from 60 to 26 mV/dec and the on-current (ION) becomes ~ 2.0 times increased as compared to the conventional Lshaped TFETs. Moreover, it is confirmed that the pocket doping effectively suppresses the corner tunneling without the on-current reduction even in the extremely scaled gate length (LG) device.

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