Design methodology for fine-grained leakage control in MTCMOS

Abstract

Multi-threshold CMOS is a popular technique for reducing standby leakage power with low delay overhead. MTCMOS designs typically use large sleep devices to reduce standby leakage at the block level. We provide a formal examination of sneak leakage paths and a design methodology that enables gate-level insertion of sleep devices for sequential and combinational circuits. A fabricated 0.13 m, dual V T testchip employs this methodology to implement a low-power FPGA core with gate-level sleep FETs and over 8X measured standby current reduction. The methodology allows local sleep regions that reduce leakage in active CLBs by up to 2.2X (measured) for some CLB configurations.

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

“…Calhoun et al [34] have proposed the creation of fine-grained "sleep region" to control the leakage current in the system. With this technique, it becomes possible to put unused LUTs and flip-flops to sleep mode independently.…”

A novel low-power FPGA routing switch

“…A number of recent studies have considered optimizing FPGA power consumption at the architecture or circuit level [2,12,5,13]. To our knowledge, the only work to specifically address leakage in FPGA interconnect is [6], which applies wellknown leakage reduction techniques to interconnect multiplexers.…”

A general post-processing approach to leakage current reduction in SRAM-based FPGAs

“…[4] uses high-V t local sleep transistors in FPGA logic blocks. These transistors give the capability to place individual regions of the logic block in sleep mode, including a group of four 4-input lookup tables (LUTs), a 4-bit adder, a 4-bit register, and the remaining control circuits.…”

“…These transistors give the capability to place individual regions of the logic block in sleep mode, including a group of four 4-input lookup tables (LUTs), a 4-bit adder, a 4-bit register, and the remaining control circuits. While this approach to ground-gating in an FPGA is similar to what we detail in this paper, the sleep transistor granularities considered in [4] were significantly more coarse, and only logic block leakage was considered. We explore a variety of granularities and show that the majority of SRAM cell leakage current savings can be derived from unused routing resources.…”