Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model

Mangla, Anurag; Chalkiadaki, Maria-Anna; Fadhuile, François; Taris, Thierry; Deval, Yann; Enz, Christian

doi:10.1016/j.mejo.2013.02.022

Cited by 33 publications

(18 citation statements)

References 12 publications

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“…The expression of the minimum noise figure (F min ) at the operating (angular) frequency (x 0 ) is reported in (12). It reveals that the increase of g m and R F decreases F min .…”

Section: Low-power Lna Designmentioning

confidence: 99%

“…2. It is low in the super-threshold region, and its maximum occurs in the sub-threshold region, which makes the latter region very attractive for power-efficient circuit design [12].…”

Section: Inversion Coefficient Approachmentioning

confidence: 99%

“…An alternative approach to the V GS -based derivation of the MOS drain current is to describe it with the inversion coefficient (IC) which is a measure of the level of channel inversion [12]. The IC, defined in (1), is the drain-current normalized to a specific current I spec for a MOS transistor in forward saturation.…”

Section: Inversion Coefficient Approachmentioning

confidence: 99%

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A low-power 2.4-GHz combined LNA–VCO structure in 0.13-µm CMOS

Taris

Rashtian

Shirazi

et al. 2014

Analog Integr Circ Sig Process

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A combined low-noise amplifier and voltagecontrolled oscillator (LNA-VCO) is implemented in a 0.13-lm CMOS technology. The low-power LC VCO and LNA circuits are stacked and share the same bias current. An LC filter is used between the LNA and the VCO to improve the isolation between the two functions. Based on the measurement results of the proof-of-concept prototype, the LNA achieves a gain of 18.4 dB and a noise figure (NF) of 3.8 dB at 2.4 GHz. The VCO has a center frequency of 2.45 GHz with a -5.3 dBm output power and a phase noise of -119 dBc/Hz at 1-MHz offset. The combined LNA-VCO block consumes 240 lW from a 0.8 V supply.

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“…The expression of the minimum noise figure (F min ) at the operating (angular) frequency (x 0 ) is reported in (12). It reveals that the increase of g m and R F decreases F min .…”

Section: Low-power Lna Designmentioning

confidence: 99%

“…2. It is low in the super-threshold region, and its maximum occurs in the sub-threshold region, which makes the latter region very attractive for power-efficient circuit design [12].…”

Section: Inversion Coefficient Approachmentioning

confidence: 99%

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A low-power 2.4-GHz combined LNA–VCO structure in 0.13-µm CMOS

Taris

Rashtian

Shirazi

et al. 2014

Analog Integr Circ Sig Process

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“…As will be shown in the second part of this paper, the transconductance efficiency (or its inverse) appears in many expressions related to the optimization of analog circuits. In normalized form, the transconductance efficiency is defined as the actual transconductance obtained at a given IC with respect to the maximum transconductance G m = I D /(nU T ) reached in WI [4], [15] …”

Section: The Transconductance Efficiency G M /I Dmentioning

confidence: 99%

“…The designer often needs to make optimum choices to achieve the required gain, current efficiency, bandwidth, linearity and noise performance [2], [3]. To this purpose, he often starts his new design using simple transistor models to explore the design space and identify the region offering the best trade-off, before fine tuning his design by running more accurate simulations using the full fetched compact model available in the design kit [4], [5]. This task has been made more difficult in advanced CMOS technologies due to the down-scaling of CMOS processes and the reduction of the supply voltage, which has progressively pushed the operating point from the traditional strong inversion (SI) region towards moderate (MI) and even weak inversion (WI), where the simple quadratic model is obviously no more valid [6], [7].…”

Section: Introductionmentioning

confidence: 99%

Nanoscale MOSFET Modeling: Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

Enz

Chicco

Pezzotta

2017

IEEE Solid-State Circuits Mag.

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Abstract-This paper presents the simplified charge-based EKV MOSFET model and shows that it can be used for advanced CMOS processes despite its very few parameters. The concept of inversion coefficient IC is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT 0 and spans the entire range of operating points from weak via moderate to strong inversion, including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40-nm and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation valid from weak to strong inversion and requiring only the VS parameter λc is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuit, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to strong inversion with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance G ds /ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for DIBL. The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted SOI (FDSOI) and FinFET 28-nm processes.

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