Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package

Muthana, P.; Engin, A. Ege; Swaminathan, Madhavan; Tummala, Rao; Sundaram, Venky; Wiedenman, B.; Amey, Daniel I.; Dietz, K.H.; Banerji, Sounak

doi:10.1109/tadvp.2007.901548

Cited by 26 publications

(9 citation statements)

References 14 publications

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“…To provide effective decoupling above 100 MHz, the total capacitance of the onchip capacitors must be increased without increasing the chip area. Another approach is to include embedded capacitors within a PCB package or thin-film circuit [22]. This decoupling solution employs discrete thick-or thin-film capacitors arranged in a capacitive array that can be used within a package to provide decoupling for high-performance circuits within the frequency range spanning 100 MHz to 2 GHz [23].…”

Section: Introductionmentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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Three-dimensional (3D) through silicon via (TSV) technologies promise increased system integration at lower cost and reduced footprint, as well as increased system bandwidth. Three-dimensional TSV may be implemented by simply adapting current silicon fabrication and package technologies. There is a strong demand for 3D, high-density and the heterogeneous integration of silicon and passive components because 3D integrated circuit (3D ICs) increase layout complexity due to the needs for additional solution space, as well as increased power density and power noise issues. To overcome the I/O speed limitation related to the above power problems in 3D ICs, on-chip decoupling capacitors and passive components used in the packaging have been implemented using TSV technologies. In this chapter, TSV decoupling schemes are introduced, showing that they have prominent advantages relative to reducing the inductive power distribution network (PDN) impedance and suppressing power noise such as the simultaneously switching noise (SSN) in the 3D ICs.

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Section: Introductionmentioning

confidence: 99%

TSV Decoupling Schemes

Song

Pak

Kim

2014

Electrical Design of Through Silicon Via

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“…1. Embedded capacitors are classified into two categories [7]: embedded planar capacitors and embedded discrete capacitors. An embedded planar capacitor consists of a thin laminate embedded in a PWB that functions both as a power-ground plane and as a parallel plate capacitor.…”

Section: Introductionmentioning

confidence: 99%

Effects of moisture absorption on the electrical parameters of embedded capacitors with epoxy-BaTiO3 nanocomposite dielectric

Alam

Azarian

Pecht

2012

J Mater Sci: Mater Electron

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In this work the effects of moisture absorption on the electrical parameters of embedded capacitors is investigated. Capacitors of two different areas embedded inside a four-layered printed wiring board were selected for this work. The dielectric was a nanocomposite of epoxy and BaTiO 3 which is common dielectric material used in embedded capacitors. These capacitors were exposed to elevated temperature and humidity conditions (85°C and 85% RH) and two parameters, capacitance and dissipation factor, were measured in situ. The diffusion of moisture in the dielectric was also modeled using the finite element method (FEM), and the changes in electrical parameters were calculated theoretically. The FEM methodology was then verified by applying it on capacitors of different dimensions.

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“…Due to steadily increasing operating frequencies and the lowering of supply voltage in digital systems, SSN is a serious concern since it can affect the performance of high-speed systems. Surface-mount capacitors provide decoupling from the kilohertz range up to several megahertz [6], but they become ineffective above 100 MHz because of the increased effect of inductance associated with these devices. A low value of parasitic inductance associated with embedded planar capacitors leads to proper functioning in the high-frequency range and also to a reduction in the required number of surface-mount capacitors.…”

Section: Introductionmentioning

confidence: 99%

Reliability of Embedded Planar Capacitors With Epoxy–$\hbox{BaTiO}_{3}$ Composite Dielectric During Temperature–Humidity–Bias Tests

Alam

Azarian

Pecht

2012

IEEE Trans. Device Mater. Relib.

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In this work, the reliability of an embedded planar capacitor with epoxy-BaTiO 3 composite dielectric was investigated under temperature-humidity-bias (THB) conditions. The temperature and humidity conditions were selected as 85 • C and 85% RH, respectively. In order to investigate the effect of an applied bias, one set of capacitors was kept unbiased, and the other set of capacitors was biased at 5 V. Capacitors of two different sizes were used to investigate the effect of area on reliability under these conditions. Three parameters-capacitance, dissipation factor, and insulation resistance-were monitored in situ every hour during the THB test, which lasted for 2000 h. Data analysis and the physical explanation of change in the electrical parameters under THB conditions are presented in this paper.

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Design, Modeling, and Characterization of Embedded Capacitor Networks for Core Decoupling in the Package

Cited by 26 publications

References 14 publications

TSV Decoupling Schemes

TSV Decoupling Schemes

Effects of moisture absorption on the electrical parameters of embedded capacitors with epoxy-BaTiO3 nanocomposite dielectric

Reliability of Embedded Planar Capacitors With Epoxy–$\hbox{BaTiO}_{3}$ Composite Dielectric During Temperature–Humidity–Bias Tests

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