Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance

Liu, Dawei; Hollis, Simon; Dymond, Harry C. P.; McNeill, Neville; Stark, Bernard H.

doi:10.1109/tcsii.2016.2530902

Cited by 44 publications

(33 citation statements)

References 12 publications

(25 reference statements)

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“…An overlapping clamping structure is used in [19] to obtain a slew-rate immunity 20 V/ns. The pulsetriggered level shifter of [10] shown in Fig. 3, uses pull-up and pull-down current mirrors to cancel the injected common mode current, whilst not disturbing the input signal.…”

Section: State Of the Art High-voltage Floating Level Shiftersmentioning

confidence: 99%

“…Finally, Yang et al [7] present a slew rate enhancement technique to achieve 120 V/ns slew rate immunity and a propagation delay of 20 ns. Transient simulation results of basic level shifter in [10]…”

Section: State Of the Art High-voltage Floating Level Shiftersmentioning

confidence: 99%

“…The pulse-triggered current-mirror-based floating level shifter of [10], whose circuit schematic is shown in Fig. 3, forms the starting point for this paper's proposed designs.…”

Section: Base-line Circuit: Pulse-triggered Current Mirror-basedmentioning

confidence: 99%

“…The paper is organised as follows: Section II reviews reported high-voltage floating level shifters. Section III analyses the pulse-triggering level shifter of [10], to establish a base line. Section IV presents a step-by-step methodology to increase slew immunity whilst maintaining sub-ns delay.…”

Section: Introductionmentioning

confidence: 99%

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A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Liu

Hollis

Stark

2019

IEEE Trans. Circuits Syst. I

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Dual-output gate drivers for switched-mode power supplies require low-side reference signals to be shifted to the switch-node potential. With the move to ultra-fast switching GaN converters, there is a commercial need to achieve switch-node slew-rates exceeding 100 V/ns, however, reported level shifters do not simultaneously achieve the required power supply slew immunities and sub-ns propagation delays. This paper presents a novel design technique to achieve the first floating voltage level shifters that deliver slew-rate immunities above 100 V/ns and subns delay in the same circuit. Step-by-step transistor-level design methods are presented. This technique is applied to improve a reported level shifter, and experimentally validated by fabricating this level shifter in a 180 nm high-voltage CMOS process. The final level shifter has zero static power consumption, and is shown to have a sub-nanosecond delay across the whole operating range, a 200 V/ns positive power-rail slew tolerance, and infinite negative slew tolerance. The measured propagation delay decreases from 722 ps with the floating ground at −1.5 V, to 532 ps for a floating ground of 45 V, and the power consumption is 30.3 pJ per transition at 45 V. It has a figure of merit of 0.06 ns/(µmV), which is an 1.7× improvement on the next best reported level shifter for this type of application.

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Section: State Of the Art High-voltage Floating Level Shiftersmentioning

confidence: 99%

Section: State Of the Art High-voltage Floating Level Shiftersmentioning

confidence: 99%

“…The pulse-triggered current-mirror-based floating level shifter of [10], whose circuit schematic is shown in Fig. 3, forms the starting point for this paper's proposed designs.…”

Section: Base-line Circuit: Pulse-triggered Current Mirror-basedmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Liu

Hollis

Stark

2019

IEEE Trans. Circuits Syst. I

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“…The propagation delay is affected only by the features of HNM1-HNM6. The 'intrinsic' delay [10] of these devices is increased with higher voltage rating, but the overall propagation delay will remain low. The slew rate tolerance is derived from the symmetric architecture with good layout matching, and we therefore anticipate it to be unaffected by the use of higher-voltage rated devices when implementing a 600 V version.…”

mentioning

confidence: 99%

Building blocks for future dual-channel GaN gate drivers: Arbitrary waveform driver, bootstrap voltage supply, and level shifter

Liu

Dymond

Wang

et al. 2019

2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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Capitalising on the high-speed switching capability of 650 V GaN FETs in power-electronic bridgelegs is challenging. Whilst active gate driving has previously been shown to help overcome adverse switching behaviour, the best results are likely to be achieved through a combination of uncompromised circuit layout and active gate driving. A fully integrated dual-channel driver would minimise external circuitry and allow power devices to be placed as close together as possible. This would facilitate simultaneous minimization of parasitic inductances in the gate-drive and power-circuit loops. Other benefits would include ease of use, lower BOM cost, and providing a step towards full integration of driver and power stage. This paper presents three circuit blocks vital to the implementation of a fully integrated dual-channel gate driver-A 100 ps resolution, digitally-controlled active gate driver IC, a sub-ns propagation delay level shifter with 200 V/ns slew-rate immunity, and a regulated bootstrap supply that maintains its output voltage regardless of any switch-node undershoot during switching events. Measurement results show the efficacy of the high-resolution active gate driver in a GaN bridge leg, and the sub-ns propagation delay of the level shifter, both fabricated in a 50 V CMOS process. Simulation results demonstrate the slew-immunity of the level shifter, and operation of the bootstrap supply. It is also inferred how to increase the voltage rating of the level-shifter and bootstrap without adversely affecting performance.

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Design of Fast-Switching Circuit Blocks

Wittmann¹

2019

Integrated High-Vin Multi-MHz Converters

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Design of 370-ps Delay Floating-Voltage Level Shifters With 30-V/ns Power Supply Slew Tolerance

Cited by 44 publications

References 12 publications

A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS

Building blocks for future dual-channel GaN gate drivers: Arbitrary waveform driver, bootstrap voltage supply, and level shifter

Design of Fast-Switching Circuit Blocks

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