Design of 4 bit flash ADC using TMCC &amp; NOR ROM encoder in 90nm CMOS technology

Hosur, Kalmeshwar N.; Dariyappa,; Shivanand,; Vijay, -; Nagesha,; Attimarad, Girish V.; Kittur, Harish M.

doi:10.1109/itact.2015.7492673

Cited by 10 publications

(1 citation statement)

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“…A Wallace tree encoder adds the number of 1s produced by 2n -1 comparators using complete adder circuitry [6][7]. Wallace Tree's in-built bubble error corrector circuit in the encoder is a key distinction between it and other systems [9][10][11]. The suggested design uses a hybrid full adder circuit because of this benefit, which improves its performance at high speed.…”

Section: Introductionmentioning

confidence: 99%

Design of Wallace Tree Encoder for Flash ADC

2023

IJETER

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Analog to digital converter plays a very important role in today’s digitized world as they have wide range of applications. Wallace tree encoder is an effective hardware implementation in VLSI circuits that is utilized for the analogue to digital conversion process. The Wallace tree encoder transforms thermometer code into binary code in an ADC. The suggested flash digital to analogue converter confirmed the energy, and speed. The proposed technique provides Less Delay, Less Power Consumption, and a lesser number of transistors compared to existing techniques. In this project, the proposed transmission gate full adder technique provide Less Delay, Less Power Consumption, Better Power Delay Product and a lesser number of transistors. The proposed encoder is made to count the 1s available to the logic gates for designing ROM encoders and fat tree conversion. The power may be conserved by building a low power, high performance Wallace tree encoder implementing transmission gate logic and modified full adders since Wallace tree encoder uses more power. The proposed system focuses at lowering the transistor count to improve power efficiency and delay comparator, and it is effective in minimizing the bubble errors. The Wallace tree encoder is designed by using transmission gate based full adder circuits. The proposed designs are designed and simulated using LTspice Tool with 45nm CMOS technology. The power consumption of the encoder circuit must be decreased in order to create a low power Flash ADC. The power consumption of this encoder changes noticeably when the internal full adder circuit is modified

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Section: Introductionmentioning

confidence: 99%