Design of a 2-bit multi valued analog-to-digital converter

Farhana, Soheli; Alam, Ahm Zahirul; Khan, Sheroz; Rahman, Md. Ataur

doi:10.1109/icom.2011.5937142

Cited by 2 publications

(3 citation statements)

References 7 publications

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“…These values are determined by different voltage or current levels on each line. 1 00 12 001 2 01 13 010 3 10 21 011 4 11 22 100 --23 101 --31 110 --32 111 --33 ---There are several designs for MVL to binary converter [10] [11]. Various forms of flash techniques are usually chosen for low-resolution converters, but the major disadvantages of the flash architecture is that the number of comparators grows exponentially with its resolution [12].…”

Section: A Mvl To Binary Convertermentioning

confidence: 99%

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Multi-valued logic test access mechanism for test time and power reduction

Nekooei

Navabi

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Test time reduction is an important objective in SoC testing. This becomes harder to achieve when power management techniques, like dynamic voltage scaling, are used, that requires a core to be tested for all its operating voltages. Coupling test time with test power consumption, due to long interconnects and switching power consumption, creates a difficult situation for SoC testing. To cope with this issue, this paper proposes a new Test Access Mechanism (TAM) that uses Multi-Valued Logic (MVL). In this structure, test data going to cores with MVL technique through the same test bus. This paper proposes Binary-MVL converters, and structure of test data on a multi-voltage test bus. This arrangement also reduces test time in multi-VDD SoCs as well. We have analyzed on crosstalk noise, area and power overhead of the proposed structure. In addition, we use IEEE 1450 -Standard Test Interface Language (STIL) to send and receive MVL signal in the Automatic Test Equipment (ATE) side. We also present a Mixed-Integer Linear Programming (MILP) model for optimal test scheduling based on our new TAM structure. Experimental results for ITC'02 benchmark highlight the effectiveness of the proposed structure.

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Section: A Mvl To Binary Convertermentioning

confidence: 99%

“…The test of core i can start while core j is currently being tested only if these cores do not share TAM wires. This constraint is captured in equation (11). The constraints in (8) and (10) …”

Section: Ln 2 Ln 13mentioning

confidence: 99%

Multi-valued logic test access mechanism for test time and power reduction

Nekooei

Navabi

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…In Ref. [10], current mode comparators are used. It is 2digit flash ADC giving multivalued (quaternary) output.…”

Section: E Memorymentioning

confidence: 99%

Ternary Analog to Digital Converter using Carbon-Nanotube FET: A Survey

Gokhale¹,

Dudam²,

Sinha³

2015

IJERT

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ADCs are important devices in communication application field. There is a requirement of efficient & highly accurate ADCs. This paper investigates possible implementation of ADCs using Ternary logic and Carbon-nanotube FET and its advantages. CNTFET is a promising device for submicron node in terms of power efficiency and leakage. Also, use of ternary logic improves the accuracy & area efficiency by using less number of interconnects. Hence, Ternary ADCs using CNTFET are appropriate for advanced system needs.

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Design of a 2-bit multi valued analog-to-digital converter

Cited by 2 publications

References 7 publications

Multi-valued logic test access mechanism for test time and power reduction

Multi-valued logic test access mechanism for test time and power reduction

Ternary Analog to Digital Converter using Carbon-Nanotube FET: A Survey

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