Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs

Sano, Masaki; Shirane, Kenta; Nishikawa, Hiroki; Kong, Xiangbo; Tomiyama, Hiroyuki; Yang, Tongxin; Ukezono, Tomoaki

doi:10.1109/isocc53507.2021.9613872

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Cited by 2 publications

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On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults

Tokai,

Akamatsu,

Yotsuyanagi

et al. 2023

2023 IEEE International Test Conference in Asia (ITC-Asia)

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On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults

Tokai,

Akamatsu,

Yotsuyanagi

et al. 2023

2023 IEEE International Test Conference in Asia (ITC-Asia)

View full text Add to dashboard Cite

ILP-Based and Heuristic Scheduling Techniques for Variable-Cycle Approximate Functional Units in High-Level Synthesis

et al. 2022

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Approximate computing is a promising approach to the design of area–power-performance-efficient circuits for computation error-tolerant applications such as image processing and machine learning. Approximate functional units, such as approximate adders and approximate multipliers, have been actively studied for the past decade, and some of these approximate functional units can dynamically change the degree of computation accuracy. The greater their computational inaccuracy, the faster they are. This study examined the high-level synthesis of approximate circuits that take advantage of such accuracy-controllable functional units. Scheduling methods based on integer linear programming (ILP) and list scheduling were proposed. Under resource and time constraints, the proposed method tries to minimize the computation error of the output value by selectively multi-cycling operations. Operations that have a large impact on the output accuracy are multi-cycled to perform exact computing, whereas operations with a small impact on the accuracy are assigned a single cycle for approximate computing. In the experiments, we explored the trade-off between performance, hardware cost, and accuracy to demonstrate the effectiveness of this work.

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Design of a 32-bit Accuracy-Controllable Approximate Multiplier for FPGAs

Cited by 2 publications

References 4 publications

On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults

On Test Pattern Generation Method for an Approximate Multiplier Considering Acceptable Faults

ILP-Based and Heuristic Scheduling Techniques for Variable-Cycle Approximate Functional Units in High-Level Synthesis

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