Design of a 75‐nW, 0.5‐V subthreshold complementary metal–oxide–semiconductor operational amplifier

Abstract

This work focuses on the subthreshold design of ultra low-voltage low-power operational amplifiers. A welldefined procedure for the systematic design of subthreshold operational amplifiers (op-amps) is introduced. The design of a 0.5-V two-stage Miller-compensated amplifier fabricated with a 0.18-mm complementary metal-oxide-semiconductor process is presented. The op-amp operates with all transistors in subthreshold region and achieves a DC gain of 70 dB and a gain-bandwidth product of 18 kHz, dissipating just 75 nW. The active area of the chip is %0.057 mm 2 . Experimental results demonstrate that well-designed subthreshold op-amps are a very attractive solution to implement sub-1-V energy-efficient applications for modern portable electronic systems. A comparative analysis with low-voltage, low-power op-amp designs available in the literature highlights that subthreshold op-amps designed according to the proposed design procedure achieve a better trade-off among speed, power, and load capacitance.

Sub-threshold, cascode compensated, bulk-driven OTAs with enhanced gain and phase-margin

“…The simulation results of proposed OTA1 and OTA2 have been compared with some of the reported works [14,16,26,32,[35][36][37][38] of weak inversion region. The well-known Figure of Merits (FoMs) shown in (30)(31)(32) have been used to compare the performance of these OTAs.…”

“…12(a) and Fig. 12 Table 6 Performance comparision of proposed OTAs to [14,16,26,32,[35][36][37][38]. [14].…”

“…Thus a single stage structure offers the gain of two-stages. This gain enhancement is achieved without any extra branch current and power consumption which ensure power efficient circuit design [33][34][35][36][37][38]. The second output stage consists of a common source PMOS driver (P 7 ) and a current source load (N 5 ).…”

Amplificador Operacional De Transconductancia Con Alto Rango Modo Común Y Bajo Consumo De Potencia

“…Esta robustés se debe a que el amplificador cuenta con dos pares diferenciales de entrada complementarios (PMOS y NMOS), que compensan las variaciones de corriente a la salida. En la tabla 2 se comparan los resultados de las simulaciones de este trabajo, con los resultados de la investigación realizada por (Magnelli, Francesco, Felice, Gregorio, Giuseppe, 2013) Y (Tripurari & Vijaya, 2015).…”

An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design

“…The design of integrated circuits with ultra-low power dissipation is becoming an essential requirement considering the fact that most of the present day applications are battery operated [1]. In addition, with the scaling of transistor dimensions in nano-scale CMOS technology, it is becoming important to design with low supply voltage for better reliability of the integrated circuits.…”