Design of a 8 bit current-steering DAC for a GSM transmitter

Abstract

An 8 bit 1GSPs DAC targeting transmitters for mobile communications terminals has been implemented in 0.18ȝm TSMC technology. A correction scheme is used for the current sources in order to achieve a SFDR greater than 50dB after layout parasitic extraction in the 10MHz bandwidth. The simulated values for INL/DNL are 0.268 LSB and 0.377 LSB respectively. A 5+3 segmented architecture is used in order to reduce glitches. At 1Gbps sample rate, the total power consumption is estimated to be 15 mW on 2.5V/1.5V analog/digital supply voltages with a total die area of 0.23 mm 2 .