Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming

Lisa, Nusrat Jahan; Babu, Hafiz Md. Hasan

doi:10.1109/vlsid.2015.46

Cited by 7 publications

(6 citation statements)

References 15 publications

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“…T-count, qubit cost, gates used and if the design produces garbage output are shown. The designs in [29] and [31] produce garbage output and must be made garbageless before use in quantum algorithms. As a result, the T-count cost is doubled and the qubit cost is increased by at least n + 1.…”

Section: A Out-of-place Qclasmentioning

confidence: 99%

“…The designs in [28] [30] and [32] have no garbage outputs and can be used as is. The design in [31] offers the lowest T-count in exchange for a O(1) increase in qubit cost compared to existing works. The designs in [28] [30] and [32] achieve the lowest qubit cost with only a modest O(1) increase in T-count compared to more T-count efficient works such as [31].…”

Section: A Out-of-place Qclasmentioning

confidence: 99%

“…The design in [31] offers the lowest T-count in exchange for a O(1) increase in qubit cost compared to existing works. The designs in [28] [30] and [32] achieve the lowest qubit cost with only a modest O(1) increase in T-count compared to more T-count efficient works such as [31]. The design in [29] has the highest resource costs of the existing works.…”

Section: A Out-of-place Qclasmentioning

confidence: 99%

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T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder

Thapliyal,

Muñoz-Coreas,

Khalus

2020

Preprint

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Quantum circuits of arithmetic operations such as addition are needed to implement quantum algorithms in hardware. Quantum circuits based on Clifford+T gates are used as they can be made tolerant to noise. The tradeoff of gaining fault tolerance from using Clifford+T gates and error correcting codes is the high implementation overhead of the T gate. As a result, the T-count performance measure has become important in quantum circuit design. Due to noise, the risk for errors in a quantum circuit computation increases as the number of gate layers (or depth) in the circuit increases. As a result, low depth circuits such as quantum carry lookahead adders (QCLA)s have caught the attention of researchers. This work presents two QCLA designs each optimized with emphasis on T-count or qubit cost respectively. In-place and out-of-place versions of each design are shown. The proposed QCLAs are compared against the existing works in terms of T-count. The proposed QCLAs for out-of-place addition achieve average T gate savings of 54.34% and 37.21%, respectively. The proposed QCLAs for in-place addition achieve average T gate savings of 72.11% and 35.87% respectively.

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Section: A Out-of-place Qclasmentioning

confidence: 99%

Section: A Out-of-place Qclasmentioning

confidence: 99%

Section: A Out-of-place Qclasmentioning

confidence: 99%

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T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder

Thapliyal,

Muñoz-Coreas,

Khalus

2020

Preprint

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“…As we know the Peres logic already, it is pretty much easier to propose this type of adder using the Peres reversible gate. The Peres full adder is already proposed (Somani, Chaudhary, & Yadav, 2016;Lisa, & Babu, 2015).…”

Section: Design Imentioning

confidence: 99%

Design and optimization of reversible look ahead carry adder and carry save adder

Bhuvaneswary¹,

Lakshmi²

2020

3C Tecnología

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A circuit is said to be reversible if inputs and the outputs are equal. Reversibility focused mainly to bring down power to zero. In modern centuries, gates with reversible logic has arose together as notable vital approaches for power optimisation based on application. Reversible logic is leading area in power consumption. Based on its application, its emerging trend in power consumption. In ideal situations, reversible circuit yield nil power. In this paper, new design of the look ahead carry adder and carry save adder designed and it is optimized with the previous existing binary logic gates. Minimizing the garbage output and replacing the binary logic gates by reversible logic gates. To develop low power circuits, reversible circuit is necessary.

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“…Low-power adder circuits are designed using a new reversible gate proposed in [19]. Using reversible gates, several adders and multipliers are designed in [20][21][22][23][24][25][26][27][28][29][30] which dissipate low-power. An FIR filter model is designed using reversible logic gates in [33].…”

Section: Introductionmentioning

confidence: 99%

NEON: Near-accurate efficient FIR Filter for ultra low-power applications

Inapurapu

Ravindra

2016

2016 International Conference on Applied Electronics (AE)

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Low-power dissipation is an imperative requirement in the design of an efficient Digital Signal Processing system which is employed in many multimedia applications such as image and video processing. Finite Impulse Response (FIR) filter is indispensable in the design of several such Digital Signal Processing (DSP) applications. The output of these applications, either an image or a video can be nearly accurate for human perception. This toleration in the loss of quality of the output can be exploited to design an energy-efficient system by using approximate computation. Moreover, the efficacy of a system can be improved multi-fold by using reversible logic which benefits in the design of ultra-low-power systems. In this paper, we propose an approximate adder using a reversible Toffoli gate and employ it in designing NEON (Near-accurate and Efficient FIR filter for ultra low-power applicatiONs). Simulation results carried out using Cadence c design tools in 45nm technology node show that the FIR Filter designed using the proposed adder gives significantly better results compared to the designs using the adders in literature. Experiment results using ISCAS benchmarks and comparison with previous methods demonstrate the effectiveness of the proposed method. In addition to producing fewer garbage outputs, the FIR filter designed using the proposed adder yields power reduction of 74%, delay reduction of 64% and Power-Delay Product reduction of 90.1%.

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Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming

Cited by 7 publications

References 15 publications

T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder

T-count and Qubit Optimized Quantum Circuit Designs of Carry Lookahead Adder

Design and optimization of reversible look ahead carry adder and carry save adder

NEON: Near-accurate efficient FIR Filter for ultra low-power applications

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