Design of a Dynamic ADC Comparator with Low Power and Low Delay Time for IoT Application

Nejadhasan, Sajad; Mehrabi-Moghadam, Zahra; Abiri, Ebrahim; Salehi, Mohammad Reza

doi:10.1007/s11277-021-09201-9

Cited by 9 publications

(4 citation statements)

References 22 publications

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“…The comparator used here is a shared CDTDL comparator; the comparison stage is implemented using a comparator that compares the input signal with a reference voltage. The comparator consists of two latch circuits that share a common tail current source that helps to reduce the offset voltage and improve the speed and accuracy of the comparator [31][32].…”

Section: Resultsmentioning

confidence: 99%

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Singh,

Tripathi,

Kumar

2024

JICS

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In this study, a high-performance 16-bit, 500 MS/s successive approximation register analog-to-digital con-verter (SAR-ADC) with variable body biasing (VBB) for re-ducing sub-threshold leakage is designed and optimized. The suggested ADC architecture makes use of a voltage threshold complementary metal-oxide-semiconductor (VTCMOS) cir-cuit with Widlar current mirror technology to efficiently con-sume 39.2 μW at an operating voltage of 1.0 V. Notably, the optimized ADC achieves outstanding performance measures, such as a signal-to-noise and distortion ratio (SNDR) of 97 dB and a total harmonic distortion (THD) of -97.97 dB, which are crucial markers of the ADC's accuracy and fidelity. An over-view of the growing need for high-resolution ADCs in contem-porary high-speed data conversion systems opens the study. The main goal of this effort is to improve overall ADC per-formance and tackle the problem of sub-threshold leakage. The Widlar current mirror technology and the VTCMOS cir-cuit are integrated for enhanced linearity, decreased current mismatch errors, and minimized leakage current. This inte-gration is highlighted in the full explanation of the ADC de-sign. The advent of the VBB approach as a successful method of leakage reduction is a significant contribution to this re-search. The theoretical foundations and workings of the VBB technique are discussed, and thorough simulations and tests are used to assess how the VBB technique affects leakage cur-rent and circuit performance. The SAR-ADC design and simulations were carried out using Cadence Virtuoso soft-ware.

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Section: Resultsmentioning

confidence: 99%

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Singh,

Tripathi,

Kumar

2024

JICS

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“…The shared charge technique boosts the comparator's speed by distributing the charge among subsequent comparison cycles and a Widlar Current Mirror circuit is integrated to it that enhances linearity and reduces current mismatch error in the design. It guarantees correct reflection of the input signal onto the capacitive array, lowering distortion and improving the ADC's overall performance [20]. The Widlar current mirror consists of a pair of transistors that precisely replicate the current by mirroring it from one to the other.…”

Section: Design Of Sar Adcmentioning

confidence: 99%

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Singh,

Tripathi,

Mahmud

2024

Eng. Res. Express

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This study gives a thorough analysis of the performance of a 45 nm CMOS process-designed 16-bit 500 MS/s successive approximation register analog-to-digital converter (SAR-ADC). 16-bit R-2R DAC double-tail dynamic latch, Widlar current method, variable body-biasing technique, sample and hold block, 16-bit SAR, and 16-bit latch are used to design proposed SAR-ADC block. The SAR-ADC design and simulations were carried out using Cadence Virtuoso software. This powerful electronic design automation (EDA) tool facilitated the design, layout, and simulation of the ADC, ensuring a comprehensive analysis of its performance characteristics. MATLAB was used for post-simulation data analysis, processing, and visualization. The proposed SAR-ADC is compared with few existing examples listed as ADS8881, LTC2380-16, ADS8344, LTC2368, and MAX11156 on the performance metrics including signal-to-noise ratio (SNR), figure of merit (FOM), total harmonic distortion (THD), resolution, delay, power consumption and Figure of Merit (FOM). This work is highlighting different aspects of the suggested architecture and demonstrates how it outperforms benchmark of ADCs in terms of power usage, SNR, THD, and FOM. A SAR-ADC attains a power consumption of 39.2 µW while operating at sampling frequency of 500 MS/s at supply voltage of 1V. The results provide fresh perspectives for potential improvements in existing work in terms of reduction in power consumption and high-speed ADC at 16-bit resolution and also Jitter is scrutinized across various stages of the SAR-ADC. The proposed low power, high speed and high-resolution SAR ADC is targeted for high-quality analog-to-digital signal conversion useful in industrial automation systems, medical devices, IoT and audio processing modules.

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“…Analysis shows that it can efficiently reduce overall uncertainty while maintaining higher network efficiency using hybrid networks. Nejadhasan et al (2022) introduced a hardware-based solution that can regulate the residual energy at a different level to reduce the transmission delay. Analysis shows that signal amplification at different voltage levels minimises the uncertainty and consumes less computational power, thus extending the overall network lifespan.…”

Section: Problem Statement and Contributionsmentioning

confidence: 99%

Delay-Conscious Service Quality Constraint in IoT Sensor Networks for Smart Farming

Gupta,

Bindal

2023

Journal of Computer Science

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The Internet of Things (IoT) offers different services for the agriculture industry, such as monitoring and analysing real-time data related to current weather conditions, water level, irrigation requirements, growth of plant disease and health status/temperature/humidity, etc.,). The performance of IoT networks may vary due to environmental conditions and operational areas (rural area/urban area/underwater). These constraints may degrade the transmission quality due to delay factors because the signal propagation may vary in these areas. IoT sensors are low-powered devices designed for longdistance communication. The transmission rate may be degraded due to the delay factor, which may cause packet loss/ congestion/collision, thus resulting in unnecessary re-transmission over the cost of network resources. To resolve the transmission delay issue, there is a need to develop a solution to ensure reliable transmission under the constraint of delay, and this study will introduce a delay-aware scheme to manage the uncertainty over IoT networks in rural and urban areas. Its performance will be analysed using different quality of service constraints (i.e., throughput/delay/residual Energy/Energy Consumption, etc.) using two different IoT-based communication standards, i.e., LoRaWAN and SigFox, with IoT sensor density variation from 100-400 IoT sensors only. For simulation, an NS-3 network simulator will be utilised.

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Design of a Dynamic ADC Comparator with Low Power and Low Delay Time for IoT Application

Cited by 9 publications

References 22 publications

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications

Delay-Conscious Service Quality Constraint in IoT Sensor Networks for Smart Farming

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Design of a Dynamic ADC Comparator with Low Power and Low Delay Time for IoT Application

Cited by 9 publications

References 22 publications

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

High-Speed 16-Bit SAR-ADC Design at 500 MS/s with Variable Body Biasing for Sub-Threshold Leakage Reduction

Design of a 16–bit 500 MS s–1 SAR-ADC at 45 nm for low power and high frequency applications

Delay-Conscious Service Quality Constraint in IoT Sensor Networks for Smart Farming

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Design of a 16–bit 500 MS s^–1 SAR-ADC at 45 nm for low power and high frequency applications