Design of a fault tolerant solid state mass memory

Abstract

Abstract-This paper describes a novel architecture of fault tolerant Solid State Mass Memory (SSMM) for satellite applications. Mass memories with low-latency time, high throughput, and storage capabilities cannot be easily implemented using space qualified components, due to the inevitable technological delay of these kind of components. For this reason, the choice of Commercial Off The Shelf (COTS) components is mandatory for this application. Therefore, the design of an electronic system for space applications, based on commercial components, must match the reliability requirements using system level methodologies [1], [2]. In the proposed architecture error-correcting codes are used to strengthen the commercial Dynamic Random Access Memory (DRAM) chips, while the system controller is developed by applying fault tolerant design solutions. The main features of the SSMM are the dynamic reconfiguration capability, and the high performances which can be gracefully reduced in case of permanent faults, maintaining part of the system functionality. This paper shows the system design methodology, the architecture, and the simulation results of the SSMM. The properties of the building blocks are described in detail both in their functionality and fault tolerant capabilities. A detailed analysis of the system reliability and data integrity is reported. The graceful degradation capability of our system allows different levels of acceptable performances, in terms of active I/O link Interfaces and storage capability. The results also show that the overall reliability of the SSMM is almost the same using different RS coding schemes, allowing a dynamic reconfiguration of the coding to reduce the latency (shorter codewords), or to improve the data integrity (longer codewords). The use of a scrubbing technique can be useful if a high SEU rate is expected, or if the data must be stored for a long period in the SSMM.The reported simulations show the behavior of the SSMM in presence of permanent and transient faults. In fact, we show that the SCU is able to recover from transient faults. On the other hand, using a spare microcontroller also hard faults can be tolerated. The distributed file system confines the unrecoverable fault effects only in a single I/O Interface. In this way, the SSMM maintains its capability to store and read data. The proposed system allows obtaining SSMM characterized by high reliability and high speed due the intrinsic parallelism of the switching matrix.

A survey of memory error correcting techniques for improved reliability

“…This is related to using a background task to inspect memory periodically for single-bit errors and does not wait for a memory access, while the ECC performs the correction after memory access. The memory scrubbing technique can be useful if a high SEU rate is expected (Cardarilli et al, 2003). ''Sparing'' techniques are also used by some designers to replace a defective component from an operating memory without requiring manual intervention (Aichelmann and Lange, 1982).…”

Extend orthogonal Latin square codes for 32-bit data protection in memory applications

“…It is more likely that a single radiation particle bit will upset multiple cells, which is known as multiple cell upsets (MCUs) [7,8]. In order to protect memories in the presence of MCUs, the interleaving technique is usually implemented by combining SEC-DED codes.…”

A method to eliminate the event accumulation problem from a memory affected by multiple bit upsets

“…Single event upsets (SEUs) [6][7][8][9] are one of the most studied effects in this category, due to its high presence in applications. Memories [10][11][12], due to their broad use and large area, are specially sensitive to radiation effects [13,14]. That is especially true for multiple bit upsets (MBUs) [15][16][17][18], whose impact accounts for a growing number of effects.…”