Design of a high‐speed‐sampling stochastic flash analog‐to‐digital converter using device mismatch

Abstract

A stochastic flash analog-to-digital converter (SF-ADC) utilizing device mismatch is designed using a 65-nm CMOS process. Since the proposed SF-ADC uses thresholds determined by the input-referred comparator offsets, large input-referred offsets are allowed. The quantization error and nonlinearity of SF-ADC are demonstrated, and the input range is enlarged by using nonlinearity reduction technique. At 1.6 GS/s sampling, the designed ADC achieves 34.7-dB SFDR and 29.0-dB SNDR without any calibration circuits despite the large input-referred offset of 102 mV. At this conversion speed, it consumes 134 mW with a 1.2-V power supply.

An offset distribution modification technique of stochastic flash ADC

“…Each offset Á OS;i ði ¼ 1; 2; Á Á Á ; N comp Þ is random and difficult to estimate, where N comp is the total number of comparators. However, the offsets are usually modeled as a Gaussian probability density function (PDF), and the standard deviation of the offsets, OS , can be estimated to some extent in the circuit design [9,15].…”

“…In previous works [9,15], the comparators with the same offset distribution were divided into two groups, and their reference voltages were assigned with V REF AE OS . In this case, the PDF of the responding comparators for the input voltage V IN is modified as…”

“…However, the SNDR for small input signal below OS degrades under the finite number of comparators due to smaller number of responding comparators [9]. To enhance linearity of the SF-ADC without SNDR degradation for small input signal below OS , a novel OSDM technique shown in Fig.…”

“…This approach has led to the proposal of stochastic flash ADCs (SFADCs), which apply the statistical nature of comparator offsets to detect signals below the offset level thereby maintain good dynamic range even in fine-process devices with substantial mismatch [8,9,10]. This technique originates from a detection principle of small signal with noise, so-called stochastic resonance [11,12,13,14].…”

“…The previous work using a 1.2-V 65-nm CMOS process [15] experimentally demonstrated basic operation for signal detection in 500 MS/s sampling. However, non-linearity of SF-ADC is still one of the most important issues even using the non-linearity reduction technique proposed in the previous work [9,15].…”