Design of a linearized and efficient doherty amplifier for C-band applications

Probst, Steffen; Martinelli, T.; Seewald, Steffen; Geck, Bernd; Manteuffel, Dirk

doi:10.23919/eumic.2017.8230675

Cited by 7 publications

(2 citation statements)

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“…As also shown in Figure 4, the separate groups of specific designs circled for UHF and SHF are not feasible if design time and hence complexity, is an important factor for the designers who are designing for gain enhancement. Employing multiple harmonic tunings done by Steffen et al [19] could reach a gain of 11dB for SHF applications but at the expense of a high NCF. On the other hand, a cascading design as demonstrated by J. Kang et al [15] might enhance the gain significantly but the designer has to weigh the trade-off with an NCF of about 10.…”

Section: Experiments and Discussionmentioning

confidence: 99%

A Simplified Methodology to Evaluate Circuit Complexity: Doherty Power Amplifier as a Case Study

et al. 2019

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This paper analyzes the circuit complexity using Doherty power amplifier (DPA) as a case study and proposes a simplistic model to characterize the design complexity of a DPA circuit. Various fundamental building blocks of the DPA circuit are discussed and modeled to formulate the model. In one of our experiments, it is observed that a reduction of up to 400% in the normalized complexity factor (NCF) could enhance the gain performance by approximately up to 40% for UHF applications. This work can be used as a common benchmarking tool to compare various types of DPA architecture and allow design teams to optimize their building blocks in the DPA circuit. This model can also potentially become a platform for the improvement of many integrated circuit design components, allowing ready integration on a wide range of next generation applications, not only limited to DPA circuits.

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Section: Experiments and Discussionmentioning

confidence: 99%

A Simplified Methodology to Evaluate Circuit Complexity: Doherty Power Amplifier as a Case Study

et al. 2019

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“…The separate groups of specific designs circled for UHF and SHF are not feasible if design time and hence complexity, is an important factor for the designers who are designing for gain enhancement. Employing multiple harmonic tunings done by Steffen et al [53] could reach a gain of 11dB for SHF applications but at the expense of a high NCF.…”

Section: Complexity Models Of Dpa Blocksmentioning

confidence: 99%

An approach for circuit design optimization based on complexity considerations

Tan¹

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Optimizing circuit trade-offs is a highly challenging task for any design team. This challenge is further exacerbated with the additional design complexity of integrating multiple circuits. Today, with the increasing demand for newer wireless communication products, design teams face a shorter time-to-market (TTM) for every generation of their new products and each product requires major improvement in wireless capability. Hence, it is important for the design teams to design circuits with complexity in mind. A design approach divided into architecture complexity, component complexity and discretional complexity are proposed. A novel benchmarking figure-of-merit, complexity factor (CF), was formulated and proposed for the architecture complexity. A simulated application of a goal, gain optimization, demonstrated and revealed that a reduction of up to 400% in the normalized complexity factor (NCF) could enhance the gain performance by approximately up to 40% for ultra-high frequency (UHF) applications. As the number of variables to be permuted is very high for the power amplifier (PA) blocks from circuit down to the process level, it is treated as a black box in the analysis but the next topology complexity step addressed this. A topology comparison was proposed between a 2-stacked EDNFET and SGNFET and a 4-stacked resistorladder SGNFET PA. Both of them achieved a near 20dBm output power and approximately 60% efficiency on the test-chips measurements, which demonstrated that the 2-stacked EDNFET and SGNFET topology with a reduction in stack height is a potential candidate for a reduced difficulty and complexity Doherty power amplifier (DPA) design. In the discretional complexity step, we explored the linearization of the DPA and proposed a DPA with a gm3 cancellation bias scheme tapping on its intrinsic linearization property, without adding external circuity to XII increase the complexity of the overall circuit but at the same time, improve its linearity by 6-8dB compared to a DPA optimized for power and more than 9dB compared with a balance PA with a similar structure. XIII

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