This paper proposes a new technique and design methodology on a transformer-based Class-E complementary metal-oxide-semiconductor (CMOS) power amplifier (PA) with only one transformer and two capacitors in the load network. An analysis of this amplifier is presented together with an accurate and simple design procedure. The experimental results are in good agreement with the theoretical analysis. The following performance parameters are determined for optimum operation: The current and voltage waveform, the peak value of drain current and drain-to-source voltage, the output power, the efficiency and the component values of the load network are determined to be essential for optimum operation. The measured drain efficiency (DE) and power-added efficiency (PAE) is over 70% with 10-dBm output power at 2.4 GHz, using a 65 nm CMOS process technology.

This paper analyzes the circuit complexity using Doherty power amplifier (DPA) as a case study and proposes a simplistic model to characterize the design complexity of a DPA circuit. Various fundamental building blocks of the DPA circuit are discussed and modeled to formulate the model. In one of our experiments, it is observed that a reduction of up to 400% in the normalized complexity factor (NCF) could enhance the gain performance by approximately up to 40% for UHF applications. This work can be used as a common benchmarking tool to compare various types of DPA architecture and allow design teams to optimize their building blocks in the DPA circuit. This model can also potentially become a platform for the improvement of many integrated circuit design components, allowing ready integration on a wide range of next generation applications, not only limited to DPA circuits.

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