Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

Kim, J. B.; Lee, Y. S.

doi:10.1080/00207210701679926

Cited by 3 publications

(1 citation statement)

References 3 publications

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“…Different digital circuits like registers, clock circuits, memory are designed using MOS Current Mode Logic circuits. Recent works are designed multiplier [14], flip flop [15,16] and registers using MOS Current Mode Logic circuits. However, it has only traditional logic gates that have issues with information loss.…”

Section: Introductionmentioning

confidence: 99%

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Devi¹,

Bhanumathi²

2022

Computers, Materials &Amp; Continua

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Now a days, MOS Current Mode Logic (MCML) has emerged as a better alternative to Complementary Metal Oxide Semiconductor (CMOS) logic in digital circuits. Recent works have only traditional logic gates that have issues with information loss. Reversible logic is incorporated with MOS Current Mode Logic (MCML) in this proposed work to solve this problem, which is used for multiplier design, D Flip-Flop (DFF) and register. The minimization of power and area is the main aim of the work. In reversible logic, the count of outputs and inputs is retained as the same value for creating one-to-one mapping. A unique output vector set can be generated for each input vector set and information loss is also prevented. In reversible MCML based multiplier, reversible logic full adder is utilized to minimize the area and power. D flip-flops based on reversible MCML are often designed to store information that is then combined to form a reversible MCML based register. The proposed reversible MCML multiplier attains average power of 0.683 mW, Reversible MCML based DFF achieves 0.56 µW and Reversible MCML based 8-bit register attains 04.04 µW. The result shows that the proposed Reversible MCML based multiplier, Reversible MCML based D flip-flop and Reversible MCML based register achieves better performance in terms of current, power dissipation, average power and area.

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Section: Introductionmentioning

confidence: 99%

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Devi¹,

Bhanumathi²

2022

Computers, Materials &Amp; Continua

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High performance 16-bit MCML multiplier

Delican

Morgul

2009

2009 European Conference on Circuit Theory and Design

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This paper presents a high performance 16x16 bit 2's complement multiplier using MOS Current Mode Logic (MCML). A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, MUX and full adder are designed and optimized for low power and high-speed operation. Using these gates, a 16 bit MCML signed multiplier is designed and tested for 4 different supply current, in a UMC 0.18 µm CMOS technology and VDD of 1.8V. According to our simulations, the highest current circuit works at 800 MHz and consumes 55 mW, while the lowest power operates at 250 MHz and consumes 16 mW. The circuits are either consume less power or operate up to a higher frequency compared to equivalent circuits in the literature. One of the most important advantages of this circuit is the absence of the power supply current spikes which makes the circuit very suitable for mixed mode designs. The multiplier consists of 7,268 transistors while a comparable CMOS multiplier in the literature consists of 13,444 transistors.

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Design of a Low-Power MOS Current-Mode Logic Circuit

Kim

2010

The KIPS Transactions:PartA

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This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The 16x16 bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung 0.18 ㎛ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

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Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

Cited by 3 publications

References 3 publications

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

Reversible Logic Based MOS Current Mode Logic Implementation in Digital Circuits

High performance 16-bit MCML multiplier

Design of a Low-Power MOS Current-Mode Logic Circuit

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