High performance 16-bit MCML multiplier

Delican, Yavuz; Morgul, A.

doi:10.1109/ecctd.2009.5274960

Cited by 12 publications

(2 citation statements)

References 7 publications

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“…However, when it is disabled, it produces a high impedance output, effectively disconnecting the output node from the power supply and ground. This feature helps to minimize power consumption in the circuit [20], [21].…”

Section: Introductionmentioning

confidence: 99%

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Madheswaran,

Panneerselvam

2024

IJPEDS

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Metal oxide semiconductor (MOS) current mode logic (MCML) is generally preferred for high-speed circuit design. In this paper, a novel low voltage folded (LVF) MCML D-Latch is designed. The existing topologies of the MCML D-Latch consume more power and operate at 1 V. The proposed D-Latch can operate at 0.6V with better delay and power management. MCML circuits minimize delay and perform fast operations, hence it can be used in high-frequency applications. The proposed LVF MCML D–Latch is analyzed with the parameters such as power, delay, power delay product and output noise using cadence virtuoso in 45 nm complementary metal oxide semiconductor (CMOS) technology at a voltage of 0.6 V and a temperature of 27 °C. The proposed technique achieves 62.11% of power reduction, transient response speed improved by 51.23% and noise cancellation becomes 26.13% improvement over the existing circuit. It also achieves 96% of output swing which is more efficient compared to others. Finally, the parametric analysis is performed with different temperatures to verify the stability of the proposed circuit. From the simulated results, it is clear that the proposed LVF MCML D-Latch provides better performance in high-speed phase locked loop (PLL) applications.

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Section: Introductionmentioning

confidence: 99%

Design of a high-speed MCML D-Latch at 0.6 V in 45 nm CMOS technology

Madheswaran,

Panneerselvam

2024

IJPEDS

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“…The power consumption of CMOS logic is proportional to frequency, while in MCML (MOS current mode logic) gate is approximately independent of frequency. The MCML structure is suitable for designing high‐performance digital circuits 3–5 . In CML, the common point of source‐coupled transistors is connected to a constant current source.…”

Section: Introductionmentioning

confidence: 99%

Low‐voltage and high‐speed stand‐alone multiple‐input complex gates for error correction coding applications

Rafiee

Ghaznavi‐Ghoushchi

2020

Circuit Theory & Apps

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Summary This paper presents two low‐voltage high‐speed shallow‐depth current mode logic (CML) topologies. The number of stacked transistors of these proposed structures decreases between VDD to GND. Reduce stacks in proposed gates enhance the circuit to operate at lower supply voltages. Therefore, the proposed logic causes to use of a stand‐alone multiple‐input gate instead of a low‐input gate. The use of decomposing multiple‐input gate for some input series causes error in the output of the circuit. In advanced technologies with size scaling down, the reliability and correctness of data in memories are essential issues. Error correction codes (ECCs) are used for protecting memories against faults. Reducing power consumption with preserving speed is vital in the design of ECCs. The units of ECCs are composed of multiple‐input gates; hence, using a low‐voltage high‐performance structure is required. The essential properties of the proposed logic are low‐voltage and high‐speed operation modes. It also gains in delay improvement of the proposed structure and multiple‐tailed current mode logic (MTCML) than source‐coupled logic (SCL) about 27% and 21% in the low‐voltage design. The final power delay product (PDP) of proposed logic and MTCML is improved by about 14% and 11% than SCL.

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