Design of a low power, high speed double tail comparator

Aakash, S.; Anisha, A.; Das, Gautam; Abhiram, T.; Anita, J. P.

doi:10.1109/iccpct.2017.8074370

Cited by 13 publications

(3 citation statements)

References 6 publications

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“…Design of New Double-Tail Comparator with Low-Power high speed having the power dissipation 38.54microW CMOS Comparators are chosen in ADCs because they have less delay and consume less power (Aakash et al 2017). Design of Low power Magnitude Comparator has the power consumption of 6.12-μm.…”

Section: Discussionmentioning

confidence: 99%

Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator

Gajawada¹,

Mohana²

2022

ECS Trans.

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The aim of the study is to construct and analyze innovative CMOS based double tail comparators and compare them with a dynamic comparator using VLSI technology. Materials and methods: The comparator is designed by using the tanner tool for simulation and verification. By varying the length of a transistors the power values were obtained. There are two groups in the study. CMOS double tail comparator is the experimental group and dynamic tail comparator is the control group. This experiment is performed for 20 different values of length. Results: The power consumption of a CMOS logic double tail comparator is 0.38035 followed by the dynamic comparator is 0.4934. Insignificance of 0.150 was obtained which is greater than (p<0.05). Conclusion: The consumption of power by the constructed CMOS logic double tail comparator appears to be less than dynamic double tail comparator.

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Section: Discussionmentioning

confidence: 99%

Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator

Gajawada¹,

Mohana²

2022

ECS Trans.

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“…It reduces to 250pS at VDD=720mV, temp. =0°C, SS process corner [14][15][16][17][18][19][20][21][22][23][24][25][26]. 790 simulation of maximum worst case condition, the average power consumption of proposed comparator is 77nW which is 87% lower than Paik's comparator and 73% lower than Schinkel's comparator.…”

Section: Functional Simulationmentioning

confidence: 99%

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Rusli

Shafie

Sidek

et al. 2020

IJEECS

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Power consumption and speed are the main criteria in designing comparator for analog-to-digital converter (ADC). This paper presents an optimized low voltage low power dynamic comparator which is robust to process, voltage and temperature (PVT) variations with adequate speed. The comparator circuit was designed using 0.18µm CMOS technology with low voltage supply of 0.8V. The method used to verify the robustness of the comparator circuit across 45 PVT is presented. The circuit is simulated with 10% voltage supply variation, five process corners and temperature variation from 0°C to 100°C. The simulation result show that the proposed comparator circuit achieved significant reduction of power consumption and delay during worst case condition compared to dynamic comparator proposed from previous researchers.

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“…As mentioned above, there are various types of comparators whose functions differ from each other, regarding specifications or design requirements. This design applies a DT comparator architecture, which was generally introduced and improved in [ 10 , 11 , 12 ]. The target was to reduce the number of comparators by half compared to the conventional flash ADC.…”

Section: Introductionmentioning

confidence: 99%

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

Thai

Pham

2022

Sensors

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This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

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Design of a low power, high speed double tail comparator

Cited by 13 publications

References 6 publications

Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator

Construction of CMOS Logic Double Tail Comparator for Lower Power Consumption Compared with Dynamic Comparator

Optimized low voltage low power dynamic comparator robust to process, voltage and temperature variation

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

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