Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementation

Abstract

This paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. The baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. The demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beamforming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using π/2 QPSK modulation with a 13/16 LDPC code rate.

Energy-proportional single-carrier frequency domain equalization for mmWave wireless communication

“…Hence single-carrier (SC) cyclic-prefix frequency domain equalization (CP-FDE) as proposed in [1] was suggested for mmWave in [2] due to its excellent equalization performance combined with reasonable complexity. Several implementations of CP-FDE for SC mmWave systems have been demonstrated [3], [4], [5]. While such CP-FDE implementations are very universal, they suffer from a constant complexity and hence operate only very energy efficient in environments with large delayspreads.…”