This paper describes the system architecture, design methodology and subsequent FPGA mapping of a millimeter wave digital baseband for wireless communication in the 60GHz spectral band. The baseband is designed to be compliant with the 802.11ad Single Carrier and Control PHY draft specifications and supports a data rate of 2.5Gbps at the physical layer. The demanding throughput and latency requirements are achieved with a parallel implementation. However, due to limited capacity of the FPGAs present in our prototype platform and complex partitioning requirements, only a scaled down version of the full single carrier baseband that operates at 1/10th the throughput of the specification could be mapped. A minimal real-time hardware MAC was also incorporated and coupled with a 60GHz RF beamforming front-end to demonstrate file transfer between two independent FPGA prototyping systems. A system throughput of 59Mbps was achieved at the application layer using π/2 QPSK modulation with a 13/16 LDPC code rate.

This paper presents a method to parallelize the meandering based 3D recursive search (3DRS) motion estimation algorithm used in scan-rate up-conversion. The proposed algorithm is scalable and can easily be mapped to multiple processing units such as multithreaded processors, multicores and/or co-processors in order to cope up with the increasingly hard to meet real time requirements of next generation video devices. Experiments show that the picture quality of the proposed parallel 3DRS algorithm is as good as the original nonparallelized algorithm for most video sequences.

Multicore architectures provide scalable performance with a lower hardware design effort than single core processors. Our article presents a design methodology and an embedded multicore architecture, focusing on reducing the software design complexity and boosting the performance density. First, we analyze characteristics of the Task-Level Parallelism in modern multimedia workloads. These characteristics are used to formulate requirements for the programming model. Then we translate the programming model requirements to an architecture specification, including a novel low-complexity implementation of cache coherence and a hardware synchronization unit. Our evaluation demonstrates that the novel coherence mechanism substantially simplifies hardware design, while reducing the performance by less than 18% relative to a complex snooping technique. Compared to a single processor core, the multicores have already proven to be more area-and energy-efficient. However, the multicore architectures in embedded systems still compete with highly efficient function-specific hardware accelerators. In this article we identify five architectural methods to boost performance density of multicores; microarchitectural downscaling, asymmetric multicore architectures, multithreading, generic accelerators, and conjoining. Then, we present a novel methodology to explore multicore design spaces, including the architectural methods improving the performance density. The methodology is based on a complex formula computing performances of heterogeneous multicore systems. Using this design space exploration methodology for HD and QuadHD H.264 video decoding, we estimate that the required areas of multicores in CMOS 45 nm are 2.5 mm 2 and 8.6 mm 2 , respectively. These results suggest that heterogeneous multicores are cost-effective for embedded applications and can provide a good programmability support.

In the digital era, communication through computer networks plays an important role. Through electronic communication, a person can make transactions or communication very quickly and practically. Sending data / messages from one place to another is much constrained by the issue of confidentiality. There are many ways you can hide data / messages that will be sent. First, using cryptographic techniques, namely by encoding data / messages using certain algorithms. Another technique is to insert a message that will be sent to other media, so that the message will be hidden and what will appear is other media used to insert messages.Here will be performed a Performance Analysis of the Combination of 3DES and DCT Algorithms in Securing Message Files into the Image.

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