Design of a pipelined adder using skew tolerant domino logic in a 0.35 μm TSMC process

Sukumar, Vinesh; Pan, Dong; Buck, Kevin; Hess, H.L.; Li, H.; Cox, D.; Mojarradi, Mohammad

doi:10.1109/wmed.2004.1297351

Cited by 2 publications

(5 citation statements)

References 4 publications

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“…Pulse latches have been used to improve the performance of general sequential circuits [24], [36], [37]. The general sequential circuits do not require slowing down the latches because in them large combinational delays are always present between the latches.…”

Section: Related Workmentioning

confidence: 99%

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms

Mansouri

Dubrova

2010

2010 IEEE International Conference on Computer Design

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In this paper, we address the problem of lowoverhead implementation of Feedback Shift Registers (FSRs). We present a dynamic pulse latch which is based on transistors with two different channel lengths. The channel lengths are selected to make the latch suitable for replacing flip-flops in FSRs. The presented latch is 1.92 times smaller and 3.94 times less power consuming compared to the smallest standard flip-flop in the same technology. By re-implementing FSRs of Grain-80 stream cipher with the presented latch, we achieve 32.24% reduction in area, 36.77% reduction in total power, and 10.81% increase in the maximum clock frequency compared to the original, flipflop based version of Grain-80. If, in addition, the static time borrowing technique is applied, we achieve an additional 25.5% increase in the maximum clock frequency at the expense of 4.68% smaller gain in area and 2.67% smaller gain in total power. 978-1-4244-8935-0/10/$26.00 ©2010 IEEE

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Section: Related Workmentioning

confidence: 99%

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms

Mansouri

Dubrova

2010

2010 IEEE International Conference on Computer Design

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“…Pipelining improves throughput at the expense of latency, however, once the pipe is filled we can expect one data item per unit of time. Some of the conventional pipelined adder designs that have been reported include one that uses overlapped clocks in an effort to eliminate sources of overhead [13]. The 4-bit carry propagate adder employs a series of three registers to equalize the delays in adding the four bits and has a three cycle latency [13].…”

Section: A Pipelined Addersmentioning

confidence: 99%

“…Some of the conventional pipelined adder designs that have been reported include one that uses overlapped clocks in an effort to eliminate sources of overhead [13]. The 4-bit carry propagate adder employs a series of three registers to equalize the delays in adding the four bits and has a three cycle latency [13]. Time borrowing is performed to shorten the critical path and the adder design has been realized in 0.35 m technology.…”

Section: A Pipelined Addersmentioning

confidence: 99%

“…A 32-bit carry-select adder in 0.25 m technology, operating at 1.67 GHz is reported in [14]. A number of pipeline registers are introduced and in a similar fashion as in [13] several of these registers are inserted in series to equalize data arrival times at adder units. The gain in speed is achieved by clocking sub-circuits faster than would be possible with a ripple carry adder.…”

Section: A Pipelined Addersmentioning

confidence: 99%

“…Introducing several registers increases the clocking overhead and skew. The adders described in [13] and [14] maybe of different types (carry propagate and carry select) however the principles leading to the use of pipelining are the same. In this paper a parallel adder is used to present the performance gains earned due to the use of hybrid wave-pipelining.…”

Section: A Pipelined Addersmentioning

confidence: 99%

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High-performance parallel addition using hybrid wave-pipelining

Levy

Nyathi

Delgado-Frias

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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Abstract-Pipelining digital systems has been shown to provide significant performance gains over non-pipelined systems and remains a standard in microprocessor design. The desire for increased performance has seen a push for deeper pipelines, as well as the introduction of pipelining schemes such as wavepipelining and hybrid wave-pipelining. In this paper we present a hybrid wave-pipelined parallel adder that operates at 1.79 GHz, ¾± performance improvement compared to that of a superpipelined adder. The simulations have been performed using a modest 0.25 m technology. The three stage hybrid wavepipelined parallel adder sustains a total of 8 unrelated data waves within the pipe. Another performance benefit achieved by using the the hybrid wave-pipelining scheme is the lessening of delays associated with clock skew and clock distribution.

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Design of a pipelined adder using skew tolerant domino logic in a 0.35 μm TSMC process

Cited by 2 publications

References 4 publications

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms

High-performance parallel addition using hybrid wave-pipelining

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