Design of a Quasi-Linear Rail-to-Rail Delay Element with an Extended Programmable Range

Abstract

This paper presents an analytical model of a quasilinear delay element to be used in the High Momentum Particle Identification Detector (HMPID) at the CERN Large Hadron Collider (LHC). The aim of this model is to facilitate the design of a delay element in order to achieve the required range while maximizing linearity. In addition, a technique is proposed to further increase the delay range by means of a programmable banked capacitor architecture without sacrificing linearity. The design of a rail-to-rail quasi-linear delay element with a range spanning from 125 ns to 580 ns was achieved. The proposed model was verified via simulations performed in Cadence using the X-FAB 0.18 µm technology.

Increasing EMI Immunity and Linearity of a CMOS 180 nm Voltage-to-Delay Converter

“…Several works can be found in the literature focused on techniques to linearize the characteristics [15][16][17][18][19]. Indeed, the linearity of VCDUs is important because it defines the dynamic range of the TMSP circuits that follow.…”

“…However, transistor sizing optimization must be performed by means of a parametric sweep in order to obtain the most linear voltage-delay characteristic: the circuit is therefore simple in the schematic but sensible to process variation. The work presented in [19] is based on the schematic discussed in [18] which is further modified and improved. It is based on a delay element controlled by a voltage Vin on a signal conditioning circuit similar to that depicted in [18] and based on a simple inverting common-source amplifier, with the pmos input device (controlled by Vin) and nmos active load (biased at Vdd) on a balanced current-starved inverter and two switches at the output connected to two capacitors.…”

“…The latter can provide a rough control of the delay, whereas Vin can precisely tune it. The power supply of the circuit in [19] is 1.8 V and the linear range goes from 0.8 V up to 1.8 V; moreover, thanks to the switchable capacitors, a wider delay range can be obtained. A comparison between the main topologies implemented to increase the linearity range of the delay cell is summarized in Table 1.…”

“…Topology Voltage Supply Linearity Range [15] 2 parallel-connected inverters 1.8 V 0.8-1.8 V [16] variable resistance and body biased 1.5 V 0.2-1.2 V [17] resistor divider and level shifter 1.8 V 0-1.2 V [18] conditioning amplifier 1.2 V 0-1.2 V [19] conditioning amplifier and sw.capacitors 1.8 V 0.8-1.8 V…”