This paper presents an analytical model of a tapped shift-register based delay generator, which is currently implemented in the High Momentum Particle Identification Detector (HMPID) at CERN and will be upgraded in the coming years. This work aims to verify whether this delay generator can be optimized to provide a delay range of 525 ns with a resolution of 1 ns. In particular, this paper studies how the clock jitter affects the delay generated and its linearity and predict how the current architecture will perform at a higher frequency of operation. The conclusions drawn via the analytical model, are then verified using both a simulation model and an FPGA implementation of the delay generator.

This paper presents an analytical model of a linear delay element circuit to be employed in the triggering module for the High Momentum Particle Identification Detector (HMPID) at the CERN Large Hadron Collider (LHC). The aim of the analytical model is to facilitate the design of the linear delay element circuit, while maximizing its linearity and delay range. The analytical model avoids the need of time consuming parametric sweeps on the aspect ratios of the various transistors of the delay element in order to optimize it. In addition, the analytical model can be used to predict the variation of the delay with the input tuning voltage. The proposed analytical model is verified via the simulation of the delay element circuit using the 0.18 µm X-FAB technology.

This paper presents an analytical model of a quasilinear delay element to be used in the High Momentum Particle Identification Detector (HMPID) at the CERN Large Hadron Collider (LHC). The aim of this model is to facilitate the design of a delay element in order to achieve the required range while maximizing linearity. In addition, a technique is proposed to further increase the delay range by means of a programmable banked capacitor architecture without sacrificing linearity. The design of a rail-to-rail quasi-linear delay element with a range spanning from 125 ns to 580 ns was achieved. The proposed model was verified via simulations performed in Cadence using the X-FAB 0.18 µm technology.

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This paper illustrates the use of the Particle Swarm Optimization (PSO) algorithm to maximize the linearity of a rail-to-rail delay element. Previous approaches relied on approximating the piecewise time-delay model of the delay element through either the Newton Polynomial or the Lagrange Polynomial methods. While adequate linearity was achieved in both cases, this could be further improved. This work successfully employed the PSO algorithm to improve the linearity by reducing the mean square error such that the delay element exhibits a spurious-free dynamic range of 29.62 dB, with a delay range of 170.4 ns. The results were verified in Cadence using the X-FAB 0.18 µm technology.