On the Design of a Linear Delay Element for the Triggering Module at CERN LHC

Abstract

This paper presents an analytical model of a linear delay element circuit to be employed in the triggering module for the High Momentum Particle Identification Detector (HMPID) at the CERN Large Hadron Collider (LHC). The aim of the analytical model is to facilitate the design of the linear delay element circuit, while maximizing its linearity and delay range. The analytical model avoids the need of time consuming parametric sweeps on the aspect ratios of the various transistors of the delay element in order to optimize it. In addition, the analytical model can be used to predict the variation of the delay with the input tuning voltage. The proposed analytical model is verified via the simulation of the delay element circuit using the 0.18 µm X-FAB technology.

Particle Swarm Optimization of a Rail-to-Rail Delay Element for Maximum Linearity

“…Malta, Malta jordan-lee.gauci.10@um.edu.mt 2 Istituto Nazionale di Fisica Nucleare, Sezione di Bari, Italy highly complex polynomial model of the circuit. However, in [3] linearity was only achieved for a limited range of…”

“…The first method is to approximate the piecewise equation of Eq. 1 by using either the Lagrange Polynomial or Newton Polynomial methods, as described in [3] and [4], respectively. While these methods can achieve good linearity, the process is cumbersome as this is done manually, while introducing a certain error due to the nature of the approximation techniques used.…”

“…In addition, it is important to have a wide delay range with a linear and monotonic transfer characteristic. This implies that rail-torail operation is essential such that the delay range is the largest possible [3].…”

“…In [3] and [4] it was shown that a quasi-linear delay can be achieved by using approximation techniques to simplify the 1…”

Design of a Quasi-Linear Rail-to-Rail Delay Element with an Extended Programmable Range

“…tp , a linear delay transfer characteristic may be achieved by setting the aspect ratios of transistors M 3 , M 5 , and M 8 to 0.9, 20.8, and 3.9, respectively. Nonetheless, since the analytical model, used for the design and optimization, is not completely valid for rail-to-rail operation [6], simulations show that the linearity worsens for V c < V t . Furthermore, this circuit is able to delay only the falling edge of the input signal, thus limiting the delay generated by the pulse width of the input.…”