Design of a Reliable p-Channel LDMOS FET With RESURF Technology

Miyoshi, T.; Tominari, T.; Fujiwara, Hiroaki; Oshima, Takayuki; Noguchi, J.

doi:10.1109/ted.2014.2309672

Cited by 23 publications

(6 citation statements)

References 12 publications

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“…3. The effective doping concentration N B of NW with the RESURF plate becomes (12) where N D is the NW doping concentration. The NW can be divided into three regions: 1) the accumulation region; 2) the drift region; and 3) the transition region by the doping concentrations.…”

Section: B Sti Demos Resurfmentioning

confidence: 99%

“…The electric field of the STI DEMOS structure can be found in the transformed 1-D domain. The breakdown model of the one-sided abrupt junction [5] along with the surface breakdown model for planar junction [6] and the optimization for reduced surface field (RESURF) LDMOS transistor [7], [12], [13] can be adopted to study the BV of STI DEMOS transistor. The BV as a function of the doping concentration, the width of the accumulation region x a , the poly plate width on STI x p , the width between the poly plate and the drain OD x d , and the STI depth y s can be derived for the STI DEMOS transistor.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors

Tsai

Yadav

Liou

et al. 2015

IEEE Trans. Electron Devices

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A CMOS compatible high-voltage shallow trench isolation (STI) drain extended MOS (DEMOS) transistor is fabricated and its electrical characteristics are studied. A local p-well (PW) plate served as a reduced surface field is adopted to enhance the breakdown voltage (BV) by reducing the effective doping concentration of the accumulation region. The conformalmapping method is used to evaluate the BV of this 2-D STI DEMOS structure theoretically. A BV model, which relates the BV to the width of the accumulation region x a and the overlap/underlap O p between the local PW plate and the STI, is derived. The predictions of this model agree very well with both the experimental data and the technology computer-aided-design simulations. Index Terms-Drain extended MOS (DEMOS), lateral doublediffused MOS (LDMOS), reduced surface field (RESURF).

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Section: B Sti Demos Resurfmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors

Tsai

Yadav

Liou

et al. 2015

IEEE Trans. Electron Devices

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“…However, due to low mobility of hole, the specific on-resistance (R on,sp ) is about 2-3 times larger than that of the n-channel LDMOS (nLDMOS). In order to reduce the R on,sp , many solutions have been proposed [15,16,17,18,19,20,21,22,23,24,25], among which the Extended Gate pLDMOS (EG-pLDMOS) [15], applying hole accumulation layer to conduct current, can significantly reduce the R on,sp . But the gate charge is dramatically increased due to that the extended gate covers the whole drift region.…”

Section: Introductionmentioning

confidence: 99%

Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer

Peng

Zhao

et al. 2020

IEICE Electron. Express

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In this letter, a high-voltage p-channel Lateral Diffused Metal Oxide Semiconductor Transistor (pLDMOS) with self-biased accumulation layer is proposed. A poly-silicon layer is formed on the thin insulator layer, which locates at the surface of the P-drift region. During on-state, an automatically obtained negative voltage is applied on the poly-silicon to induce a hole accumulation layer at the surface of the P-drift region. Therefore, the specific on-resistance (R on,sp) can be significantly reduced. Moreover, the permittivity of the gate insulator on the P-drift can be increased by selecting different insulator materials. Thus, the R on,sp can be further reduced due to more holes being accumulated at the surface of the P-drift. The simulation results shows that the R on,sp of the proposed pLDMOS can be dramatically reduced by 62.3% to 82.5% compared with that of the p-type Triple RESURF silicon limit. For the proposed pLDMOS, the transient Figure of Merit (FOM) is significantly improved by several to 10 times and the static Figure of Merit (FOM) is improved by several times compared with those of an Extended Gate pLDMOS (EG-pLDMOS) and a conventional pLDMOS.

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“…High-Voltage (HV) Lateral-Diffused Metal-Oxide-Semiconductor (LDMOS) devices are the dominant technology used in many applications nowadays, such as communication modules, power electronics components, power management circuits, automotive electronics, LCD drivers [1]- [7], its importance is increased in the HV purposes. Due to its high operating voltage, it needs to have a good reliability.…”

Section: Introductionmentioning

confidence: 99%

Design of Reliability Improvement in HV p-Channel LDMOS DUTs by a 0.25μm 60-V BCD Process

Chen¹,

Huang²

2016

IJEEE

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Different drain-side layout patterns for the 0.25m 60-V high voltage p-channel Lateral-Diffused MOS device (pLDMOS) devices are investigated in this paper. For the anti-ESD capability evaluation, a drain-side "pnp" arranged-type for a pLDMOS-embedded-SCR structure is used to study this layout type's effect. Here, the layout types of P + region will be treated as some Continuous-Extended (CE) type into the drain-side manners and some Discrete-Distributed (DD) areas into the drain-side architectures, respectively. After all, from Transmission-Line Pulse (TLP) experimental data, it can be found that the DD-type layout manners in the drain-side have a better anti-ESD capability than that of the CE-type, and the secondary breakdown current (I t2) values can be achieved above 7A (so good their are). On the other hand, the holding voltage (V h) for the latch-up consideration of the CE-type shows an escalating trend, so it will be with higher anti-electrical-over-stress (EOS) capability.  Index Terms-Electrical-Over-Stress (EOS), Electrostatic Discharge (ESD), embedded-SCR, holding voltage (V h), pchannel-lateral-diffused MOS (pLDMOS), secondary breakdown current (I t2), Transmission-Line Pulse (TLP), trigger voltage (V t1)

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Design of a Reliable p-Channel LDMOS FET With RESURF Technology

Cited by 23 publications

References 12 publications

Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors

Breakdown Voltage Model and Electrical Characteristics of CMOS Compatible RESURF STI Drain Extended MOS Transistors

Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer

Design of Reliability Improvement in HV p-Channel LDMOS DUTs by a 0.25μm 60-V BCD Process

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