Design of a Two-Step Low-Power and High-Speed CMOS Flash ADC Architecture

Kumar, S. Deepak; Ch, Nagesh

doi:10.1109/vdat50263.2020.9190433

Cited by 6 publications

(9 citation statements)

References 5 publications

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“…A fair comparison of energy and latency requires both designs to be implemented in the same technology, in this work 14 nm FinFET. In the literature, most designs employ either larger technology nodes (e.g., 180 nm Kumar and Ch (2020) or use different ADC designs with a higher resolution (e.g., 16-bit SAR-ADC Luu et al (2018). Comparing our SPICE simulation results with measurements from a fabricated device Nam and Cho ( 2021) is also misleading since the latter contains layout parasitics and other factors not considered by our simulations.…”

Section: Comparison With Related Workmentioning

confidence: 93%

“…The synapses are programmed with an increasing V TH so that synapse "1" has the lowest and synapse "N" the highest V TH . Hence, similar to a flash ADC Kumar and Ch (2020), each synapse detects a different threshold. All gates of the FeFET-based synapses are connected and subject to the same V G .…”

Section: N-way Synaptic Comparatormentioning

confidence: 99%

“…The Hamming distance is determined by the highest distance represented by any of the activated synapses. This interpretation of the outputs by the comparators is common practice in conventional flash ADC designs, wherefore we adopt it here as well Kumar and Ch (2020). Due to the variability-induced errors, the highest activated synapse is not necessarily the Hamming distance.…”

Section: Process Variation Effects and Error Probability Modelingmentioning

confidence: 99%

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All-in-Memory Brain-Inspired Computing Using FeFET Synapses

et al. 2022

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The separation of computing units and memory in the computer architecture mandates energy-intensive data transfers creating the von Neumann bottleneck. This bottleneck is exposed at the application level by the steady growth of IoT and data-centric deep learning algorithms demanding extraordinary throughput. On the hardware level, analog Processing-in-Memory (PiM) schemes are used to build platforms that eliminate the compute-memory gap to overcome the von Neumann bottleneck. PiM can be efficiently implemented with ferroelectric transistors (FeFET), an emerging non-volatile memory technology. However, PiM and FeFET are heavily impacted by process variation, especially in sub 14 nm technology nodes, reducing the reliability and thus inducing errors. Brain-inspired Hyperdimensional Computing (HDC) is robust against such errors. Further, it is able to learn from very little data cutting energy-intensive transfers. Hence, HDC, in combination with PiM, tackles the von Neumann bottleneck at both levels. Nevertheless, the analog nature of PiM schemes necessitates the conversion of results to digital, which is often not considered. Yet, the conversion introduces large overheads and diminishes the PiM efficiency. In this paper, we propose an all-in-memory scheme performing computation and conversion at once, utilizing programmable FeFET synapses to build the comparator used for the conversion. Our experimental setup is first calibrated against Intel 14 nm FinFET technology for both transistor electrical characteristics and variability. Then, a physics-based model of ferroelectric is included to realize the Fe-FinFETs. Using this setup, we analyze the circuit’s susceptibility to process variation, derive a comprehensive error probability model, and inject it into the inference algorithm of HDC. The robustness of HDC against noise and errors is able to withstand the high error probabilities with a loss of merely 0.3% inference accuracy.

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Section: Comparison With Related Workmentioning

confidence: 93%

Section: N-way Synaptic Comparatormentioning

confidence: 99%

Section: Process Variation Effects and Error Probability Modelingmentioning

confidence: 99%

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All-in-Memory Brain-Inspired Computing Using FeFET Synapses

et al. 2022

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“…Requirements should be met regarding power and resource-saving but must make sure the ADC works a high speed. After researching various types of comparator architecture, it was decided that this paper would follow the comparator structure presented in [ 13 ]. A general view of a full N-bit flash ADC is suggested in Figure 3 .…”

Section: Design and Implementationmentioning

confidence: 99%

“…The target was to reduce the number of comparators by half compared to the conventional flash ADC. The presented design [ 13 ] generates the most significant bit (MSB) with a switched reference voltage. With just a single comparator, the MSB is decided upon to depend on the input signal.…”

Section: Introductionmentioning

confidence: 99%

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

Thai

Pham

2022

Sensors

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This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

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