Design of a Wide-Band Voltage-Controlled Ring Oscillator Implemented in 180 nm CMOS Technology

Tlelo‐Cuautle, Esteban; Castañeda-Aviña, Perla Rubi; Trejo-Guerra, R.; Carbajal-Gomez, Victor Hugo

doi:10.3390/electronics8101156

Cited by 13 publications

(10 citation statements)

References 27 publications

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“…Another kind of typical analog building block is the VCO. Recently, some novel structures are proposed [37], [38]. Hence, the fourth test case is a distributed-input VCO [37] implemented in a 40 nm technology (Fig.…”

Section: Case Studymentioning

confidence: 99%

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

Budak

Gandara

Shi

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Machine learning-assisted global optimization methods for speeding up analog integrated circuit sizing is attracting much attention. However, often a few typical analog IC design specifications are considered in most relevant research. When considering the complete set of specifications, two main challenges are yet to be addressed: (1) The prediction error for some performances may be large and the prediction error is accumulated by many performances. This may mislead the optimization and fail the sizing, especially when the specifications are stringent. (2) The machine learning cost could be high considering the number of specifications, considerably canceling out the time saved. A new method, called Efficient Surrogate Model-assisted Sizing Method for High-performance Analog Building Blocks (ESSAB), is proposed in this paper to address the above challenges.The key innovations include a new candidate design ranking method and a new artificial neural network model construction method for analog circuit performances. Experiments using two amplifiers and a comparator with a complete set of stringent design specifications show the advantages of ESSAB.

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Section: Case Studymentioning

confidence: 99%

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

Budak

Gandara

Shi

et al. 2022

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Although CMOS architectures are largely used for their low static-power dissipation and high integration density, the designed RO-VCO is composed of three CML stages. The current mode logic architecture, based only on n-MOSFETs and resistors, is more suitable for high-frequency applications, thanks to their lower voltage swing and lower output impedance than a standard CMOS approach [ 16 , 17 ]. Moreover, the use of a differential structure allows obtaining higher common-mode disturb immunity than the use of a single-ended structure, as in classic CMOS circuits [ 18 ].…”

Section: Ring Oscillator Based On a Cascade Of Three Current Mode mentioning

confidence: 99%

Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

Monda

Ciarpi

Saponara

2020

Sensors

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This work presented a comparison between two Voltage Controlled Oscillators (VCOs) designed in 65 nm CMOS technology. The first architecture based on a Ring Oscillator (RO) was designed using three Current Mode Logic (CML) stages connected in a loop, while the second one was based on an LC-tank resonator. This analysis aimed to choose a VCO architecture able to be integrated into a rad-hard Phase Locked Loop. It had to meet the requirements of the SpaceFibre protocol, which supports frequencies up to 6.25 GHz, for space applications. The full custom schematic and layout designs are shown, and Single Event Effect simulations results, performed with a double exponential current pulses generator, are presented in detail for both VCOs. Although the RO-VCO performances in terms of technology scaling and high-integration density were attractive, the simulations on the process variations demonstrated its inability to generate the target frequency in harsh operating conditions. Instead, the LC-VCO highlighted a lower influence through Process-Voltage-Temperature simulations on the oscillation frequency. Both architectures were biased with a supply voltage of 1.2 V. The achieved results for the second architecture analyzed were attractive to address the requirements of the new SpaceFibre aerospace standard.

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“…In other work, a three stage VCO using differential pair NMOS and PMOS load transistor composed delay cell is presented but consumes large power [7]. When VCO is implemented using CMOS current-mode logic stages, frequency range is widened by using ring oscillator structure, but power consumption is very high [8]. To obtain a low power phase frequency detector and wide frequency range ring based VCO with low power consumption is one of the great challenges in the previous works.…”

Section: Introductionmentioning

confidence: 99%

Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

Srivastava¹,

Chauhan²

2021

JUSST

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A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

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Design of a Wide-Band Voltage-Controlled Ring Oscillator Implemented in 180 nm CMOS Technology

Cited by 13 publications

References 27 publications

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization

Analysis and Comparison of Rad-Hard Ring and LC-Tank Controlled Oscillators in 65 nm for SpaceFibre Applications

Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

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