Design of an Advanced CMOS Power Amplifier

Abstract

The CMOS power amplifier (PA) is a promising solution for highly-integrated transmitters in a single chip. However, the implementation of PAs using the CMOS process is a major challenge because of the inferior characteristics of CMOS devices. This paper focuses on improvements to the efficiency and linearity of CMOS PAs for modern wireless communication systems incorporating high peak-toaverage ratio signals. Additionally, an envelope tracking supply modulator is applied to the CMOS PA for further performance improvement. The first approach is enhancing the efficiency by waveform engineering. In the second approach, linearization using adaptive bias circuit and harmonic control for wideband signals is performed. In the third approach, a CMOS PA with dynamic auxiliary circuits is employed in an optimized envelope tracking (ET) operation. Using the proposed techniques, a fully integrated CMOS ET PA achieves competitive performance, suitable for employment in a real system.

Review of Ka-Band Power Amplifier

“…[49], a high linearity PA with ultra-wide video bandwidth for 5G wireless communication was proposed. With the increase in operating frequency, the output power, efficiency and linearity of Pas decrease sharply because of the sideband asymmetry of Pas caused by the memory effect [50]. Since third-order intermodulation distortion (IMD3) is generated by the mixing of fundamental wave and envelope nonlinear term, when the impedance at the envelope frequency is not zero, there is a large IMD3 on one side of the signal, resulting in an asymmetric IMD3 sideband [51].…”