Design of an analogue ASIC using subthreshold CMOS transistors to model biological neurons

Alvado, Ludovic; Tomas, Jean; Masson, Sylvie Renaud-Le; Douence, Vincent

doi:10.1109/cicc.2001.929732

Cited by 6 publications

(3 citation statements)

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“…One of the common approaches for analog neuromorphic systems is to utilize circuitry that operates in subthreshold mode, typically for power efficiency purposes [101], [325], [330], [334], [373], [576], [577], [641], [647], [654], [665], [684], [700], [704], [704], [720], [721], [727], [737], [1045], [1079], [1080], [1084], [1089], [1160]- [1163], [1274], [1394], [1411], [1596]- [1619]. In fact, the original neuromorphic definition by Carver Mead referred to analog circuits that operated in subthreshold mode [1].…”

Section: A High-levelmentioning

confidence: 99%

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Schuman¹,

Potok²,

Patton³

et al. 2017

Preprint

176

180

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Neuromorphic computing has come to refer to a variety of brain-inspired computers, devices, and models that contrast the pervasive von Neumann computer architecture. This biologically inspired approach has created highly connected synthetic neurons and synapses that can be used to model neuroscience theories as well as solve challenging machine learning problems. The promise of the technology is to create a brainlike ability to learn and adapt, but the technical challenges are significant, starting with an accurate neuroscience model of how the brain works, to finding materials and engineering breakthroughs to build devices to support these models, to creating a programming framework so the systems can learn, to creating applications with brain-like capabilities. In this work, we provide a comprehensive survey of the research and motivations for neuromorphic computing over its history. We begin with a 35-year review of the motivations and drivers of neuromorphic computing, then look at the major research areas of the field, which we define as neuro-inspired models, algorithms and learning approaches, hardware and devices, supporting systems, and finally applications. We conclude with a broad discussion on the major research topics that need to be addressed in the coming years to see the promise of neuromorphic computing fulfilled. The goals of this work are to provide an exhaustive review of the research conducted in neuromorphic computing since the inception of the term, and to motivate further work by illuminating gaps in the field where new research is needed.

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Section: A High-levelmentioning

confidence: 99%

A Survey of Neuromorphic Computing and Neural Networks in Hardware

Schuman¹,

Potok²,

Patton³

et al. 2017

Preprint

176

180

View full text Add to dashboard Cite

show abstract

“…Hodgkin-Huxley equations in silicon. Almost all the implementations use the Hodgkin-Huxley (H-H) formalism, some of them using a set of equations simpler than the original H-H equations [18] [77] while others have modeled in detail the full set of equations [69] [95] [2] [40] [96]. However, the principle of this design is based on similarities between voltage clamp experiments on transistor channels and biological ion channels [37].…”

Section: Hodgkin-huxley Type Dynamics There Have Been Multiple Instan...mentioning

confidence: 99%

“…All switches can be programmed in an analog way leading to around 50000 parameters. The CABs have 460 parameters 2. Minimum complexity of CAB considered to be 4 programmable transconductors similar to this work.…”

mentioning

confidence: 99%

Neural Dynamics in Reconfigurable Silicon

Basu

Ramakrishnan

Petre

et al. 2010

IEEE Trans. Biomed. Circuits Syst.

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A neuromorphic analog chip is presented that is capable of implementing massively parallel neural computations while retaining the programmability of digital systems. We show measurements from neurons with Hopf bifurcations and integrate and fire neurons, excitatory and inhibitory synapses, passive dendrite cables, coupled spiking neurons, and central pattern generators implemented on the chip. This chip provides a platform for not only simulating detailed neuron dynamics but also uses the same to interface with actual cells in applications such as a dynamic clamp. There are 28 computational analog blocks (CAB), each consisting of ion channels with tunable parameters, synapses, winner-take-all elements, current sources, transconductance amplifiers, and capacitors. There are four other CABs which have programmable bias generators. The programmability is achieved using floating gate transistors with on-chip programming control. The switch matrix for interconnecting the components in CABs also consists of floating-gate transistors. Emphasis is placed on replicating the detailed dynamics of computational neural models. Massive computational area efficiency is obtained by using the reconfigurable interconnect as synaptic weights, resulting in more than 50 000 possible 9-b accurate synapses in 9 mm(2).

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