Design of an efficient 8-bit flash ADC for optical communication receivers

Hussain, Sarfraz; Kumar, Manish

doi:10.1109/iceeot.2016.7755560

Cited by 6 publications

(4 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The total number of gates required for the optimised Fat-Tree encoder is mentioned in (11) Table 7. It can be concluded that Fat-Tree encoder is faster than MUX based encoder but consumes more power [2,11,16,18]. A modified form of Fat-Tree encoder is discussed in Section 3.3 exhibiting better performance…”

Section: Fat-tree Encodermentioning

confidence: 99%

“…Dynamic powerdissipation and leakage power dissipation are 3.42 mW and 5.55 nW, respectively.The comparison of Fat‐Tree encoder with other encoders is presented inTable 7. It can be concluded thatFat‐Tree encoder is faster than MUX based encoder but consumes more power [2, 11, 16, 18]. A modified form of Fat‐Tree encoder is discussed inSection 3.3 exhibiting better performance

\begin{matrix} right leftthickmathspace.5em \\ T_{FATencoder} \\ = n \times \{2^{n - 1} \times INVERTER \\ + (2^{n - 1} - 1 + 2^{n - 2} {false\sum}_{i = 0}^{n - 3} (\frac{1}{2^{2 i}})) \times NAND gate \\ + (2^{n - 3} {false\sum}_{i = 0}^{n - 4} (\frac{1}{2^{2 i}})) \times NOR gate\} \\ - \{[3 \times (1 + 4 \times {false\sum}_{i = 1}^{n - 3} i) + {(2}^{n - 1} - 2) - (n - 2) \\ \times NAND gate] + {false\sum}_{i = 1}^{n - 3} i \times NOR gate\} \\ = 32 \times INVERTER + 48 \times NAND gate \\ + 8 \times NOR gate - 19 \times NAND gate \end{matrix}

…”

Section: ‐Bit Encodermentioning

confidence: 99%

“…Flash analogue‐to‐digital converter (ADC) is known to be the fastest ADC because of its parallel computations. The drawback of such an ADC is the power consumption [1, 2]. Comparator and encoder are two main components of a flash ADC.…”

Section: Introductionmentioning

confidence: 99%

“…Pseudo‐NMOS based encoder [10] is fast but has a large PMOS load which increases with the increase in number of inputs. MUX based encoder [12, 13] is power efficient but slow as compared to Fat‐Tree encoder [1, 2, 16–18]. Wallace tree encoder [8] contains full adder blocks which is efficient in terms of error free transmission, but it is slower and consumes more power than fat tree encoder.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Methodology and comparative design of an efficient 4‐bit encoder with bubble error corrector for 1‐GSPS flash type ADC

Hussain

Kumar

Trivedi

2020

IET Circuits, Devices & Systems

Self Cite

View full text Add to dashboard Cite

The design of a 4-bit encoder with a bubble error correction of first order is described in this study. Since encoder restricts speed of the flash analogue-to-digital converter (ADC), therefore, an improved and faster encoder is an essential requirement to push its limits. Encoder is divided into two parts: one-hot code generator [or bubble error corrector (BEC)] and binary encoder. Binary encoder proposed in this study is the modified Fat-Tree encoder of types I and II. Three types of BECs which have been compared in this study are OR gate based, NAND gate based and the proposed BEC. The proposed BEC consumes less power and provides better speed as compared to NAND based and OR gate based BECs. It can be further employed for higher order bubble correction as well. The proposed BEC consumes dynamic power of 87.071 μW and leakage power of 18.3563 pW exhibiting the delay of 38.3 ps with 1.8 V supply voltage and 1 GHz clock frequency. It has a power-delay product of 3.335 fJ, energy-delay product of 127.7305 Js and an intrinsic area of 4.753 mm 2 .

show abstract

Section: Fat-tree Encodermentioning

confidence: 99%